Inventor

Ying Zhang

Inventor

Yorktown Heights, NY, US

Overview

1997–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 156 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices25%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%

H01LSemiconductor devices14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H01JElectric discharge tubes or discharge lamps5%

C23CCoating metallic material3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

Y10TTechnical subjects covered by former us classification3%

B82YSpecific uses or applications of nanostructures2%

B81BMicrostructural devices or systems, e.g. micromechanical devices1%

PatentTitleYear

11,038,705Fast recovery of multicast router ports on spanning tree protocol (STP) topology change in a layer 2 (L2) network2021 11,038,695Managing blockchain-based centralized ledger systems2021 10,840,138Selectively etched self-aligned via processes2020 10,796,888Ion assisted deposition for rare-earth oxide based thin film coatings on process rings2020 10,770,568Method to remove III-V materials in high aspect ratio structures2020 10,741,393Methods for bottom up fin structure formation2020 10,692,728Use of selective aluminum oxide etch2020 10,600,688Methods of producing self-aligned vias2020 10,593,594Selectively etched self-aligned via processes2020 10,573,555Methods of producing self-aligned grown via2020 10,553,485Methods of producing fully self-aligned vias and contacts2020 10,522,404Fully self-aligned via2019 10,510,540Mask scheme for cut pattern flow with enlarged EPE window2019 10,510,602Methods of producing self-aligned vias2019 10,453,684Method for patterning a material layer with desired dimensions2019 10,439,047Methods for etch mask and fin structure formation2019 10,424,507Fully self-aligned via2019 10,418,229Aerosol deposition coating for semiconductor chamber components2019 10,410,921Fully self-aligned via2019 10,269,647Self-aligned EPI contact flow2019 10,204,781Methods for bottom up fin structure formation2019 10,133,652Debugging optimized code using FAT binary2018 9,978,596Self-aligned multiple spacer patterning schemes for advanced nanometer technology2018 9,940,218Debugging optimized code using fat binary2018 9,891,189'Techniques for fabricating horizontally aligned nanochannels for microfluidics and biosensors'2018 9,869,012'Ion assisted deposition for rare-earth oxide based coatings'2018 9,818,621'Cyclic oxide spacer etch process'2017 9,812,341'Rare-earth oxide based coatings based on ion assisted deposition'2017 9,799,491'Low electron temperature etch chamber with independent control over plasma density, radical composition and ion energy for atomic precision etching'2017 9,797,037'Ion beam sputtering with ion assisted deposition for coatings on chamber components'2017 9,728,623'Replacement metal gate transistor'2017 9,725,799'Ion beam sputtering with ion assisted deposition for coatings on chamber components'2017 9,721,807'Cyclic spacer etching process with improved profile control'2017 9,708,713'Aerosol deposition coating for semiconductor chamber components'2017 9,711,334'Ion assisted deposition for rare-earth oxide based thin film coatings on process rings'2017 9,660,054'Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same'2017 9,643,179'Techniques for fabricating horizontally aligned nanochannels for microfluidics and biosensors'2017 9,583,369'Ion assisted deposition for rare-earth oxide based coatings on lids and nozzles'2017 9,564,297'Electron beam plasma source with remote radical source'2017 9,553,147'Trench formation with CD less than 10nm for replacement fin growth'2017 9,548,201'Self-aligned multiple spacer patterning schemes for advanced nanometer technology'2017 9,530,637'Fin structure formation by selective etching'2016 9,508,831'Method for fabricating vertically stacked nanowires for semiconductor applications'2016 9,478,433'Cyclic spacer etching process with improved profile control'2016 9,431,266'Double patterning method'2016 9,431,252'Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same'2016 9,419,107'Method for fabricating vertically stacked nanowires for semiconductor applications'2016 9,412,603'Trimming silicon fin width through oxidation and etch'2016 9,401,310'Method to form trench structure for replacement channel growth'2016 9,373,546'Self aligned replacement Fin formation'2016 9,343,354'Middle of line structures and methods for fabrication'2016 9,290,848'Anisotropic etch of copper using passivation'2016 9,287,386'Method for fabricating vertically stacked nanowires for semiconductor applications'2016 9,252,023'Etching method and apparatus'2016 9,252,250'Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same'2016 9,245,791'Method for fabricating a contact'2016 9,214,377'Methods for silicon recess structures in a substrate by utilizing a doping layer'2015 9,209,279'Self aligned replacement fin formation'2015 9,153,444'Process flow for replacement metal gate transistors'2015 9,105,583'Catalytic etch with magnetic direction control'2015 9,006,108'Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors'2015 8,999,794'Self-aligned source and drain structures and method of manufacturing same'2015 9,000,494'Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch'2015 8,993,419'Trench formation with CD less than 10 NM for replacement Fin growth'2015 8,993,425'Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same'2015 8,927,377'Methods for forming FinFETs with self-aligned source/drain'2015 8,901,619'Asymmetric FinFET devices'2014 8,890,318'Middle of line structures'2014 8,889,562'Double patterning method'2014 8,853,025'FinFET/tri-gate channel doping for multiple threshold voltage tuning'2014 8,829,625'Nanowire FET with trapezoid gate structure'2014 8,809,171'Methods for forming FinFETs having multiple threshold voltages'2014 8,785,281'CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials'2014 8,753,912'Nano/microwire solar cell fabricated by nano/microsphere lithography'2014 8,716,798'Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors'2014 8,673,735'Semiconductor device and method for making same'2014 8,569,868'Device having and method for forming fins with multiple widths'2013 8,557,341'Patterning structures using deformable substrates'2013 8,525,235'Multiplying pattern density by single sidewall imaging transfer'2013 8,481,389'Method of removing high-K dielectric layer on sidewalls of gate structure'2013 8,449,781'Selective etch back process for carbon nanotubes intergration'2013 8,445,948'Gate patterning of nano-channel devices'2013 8,440,523'Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch'2013 8,431,995'Methodology for fabricating isotropically recessed drain regions of CMOS transistors'2013 8,354,331'Multiplying pattern density by single sidewall imaging transfer'2013 8,343,877'Angle ion implant to re-shape sidewall image transfer patterns'2013 8,324,036'Device having and method for forming fins with multiple widths for an integrated circuit'2012 8,324,058'Contacts for FET devices'2012 8,318,570'Enhancing MOSFET performance by optimizing stress properties'2012 8,298,881'Nanowire FET with trapezoid gate structure'2012 8,268,729'Smooth and vertical semiconductor fin structure'2012 8,263,446'Asymmetric FinFET devices'2012 8,242,560'FinFET with thin gate dielectric layer'2012 8,232,171'Structure with isotropic silicon recess profile in nanoscale dimensions'2012 8,211,735'Nano/microwire solar cell fabricated by nano/microsphere lithography'2012 8,202,780'Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions'2012 8,198,103'Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist'2012 8,178,382'Suspended germanium photodetector for silicon waveguide'2012 8,158,481'CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials'2012 8,084,825'Trilayer resist scheme for gate etching applications'2011 8,053,809'Device including high-K metal gate finfet and resistive structure and method of forming thereof'2011 8,021,949'Method and structure for forming finFETs with multiple doping regions on a same chip'2011 8,003,455'Implantation using a hardmask'2011 7,935,637'Resist stripping methods using backfilling material layer'2011 7,928,443'Method and structure for forming strained SI for CMOS devices'2011 7,923,786'Selective silicon-on-insulator isolation structure and method'2011 7,923,782'Hybrid SOI/bulk semiconductor transistors'2011 7,902,620'Suspended germanium photodetector for silicon waveguide'2011 7,863,124'Residue free patterned layer formation method applicable to CMOS structures'2011 7,833,849'Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode'2010 7,820,552'Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack'2010 7,820,555'Method of patterning multilayer metal gate structures for CMOS devices'2010 7,816,275'Gate patterning of nano-channel devices'2010 7,785,944'Method of making double-gated self-aligned finFET having gates of different lengths'2010 7,785,943'Method for forming a multi-gate device with high k dielectric for channel top surface'2010 7,767,503'Hybrid SOI/bulk semiconductor transistors'2010 7,749,842'Structures and methods for making strained MOSFETs'2010 7,741,181'Methods of forming mixed gate CMOS with single poly deposition'2010 7,732,874'FinFET structure using differing gate dielectric materials and gate electrode materials'2010 7,700,951'Method and structure for forming strained Si for CMOS devices'2010 7,671,421'CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials'2010 7,659,153'Sectional field effect devices and method of fabrication'2010 7,550,338'Method and structure for forming strained SI for CMOS devices'2009 7,542,330'SRAM with asymmetrical pass gates'2009 7,498,640'Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby'2009 7,452,761'Hybrid SOI-bulk semiconductor transistors'2008 7,435,652'Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET'2008 7,435,671'Trilayer resist scheme for gate etching applications'2008 7,429,752'Method and structure for forming strained SI for CMOS devices'2008 7,413,941'Method of fabricating sectional field effect devices'2008 7,388,258'Sectional field effect devices'2008 7,388,257'Multi-gate device with high k dielectric for channel top surface'2008 7,348,641'Structure and method of making double-gated self-aligned finFET having gates of different lengths'2008 7,344,965'Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions'2008 7,326,983'Selective silicon-on-insulator isolation structure and method'2008 7,247,912'Structures and methods for making strained MOSFETs'2007 7,211,490'Ultra thin channel MOSFET'2007 7,129,126'Method and structure for forming strained Si for CMOS devices'2006 7,105,391'Planar pedestal multi gate device'2006 7,081,397'Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow'2006 6,939,751'Method and manufacture of thin silicon on insulator (SOI) with recessed channel'2005 6,936,522'Selective silicon-on-insulator isolation structure and method'2005 6,914,303'Ultra thin channel MOSFET'2005 6,876,040'Dense SRAM cells with selective SOI'2005 6,869,899'Lateral-only photoresist trimming for sub-80 nm gate stack'2005 6,864,041'Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching'2005 6,743,686'Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication'2004 6,645,861'Self-aligned silicide process for silicon sidewall source and drain contacts'2003 6,527,856'Method for changing surface termination of a perovskite oxide substrate surface'2003 6,528,363'Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch'2003 6,518,136'Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication'2003 6,429,091'Patterned buried insulator'2002 6,420,274'Method for conditioning process chambers'2002 6,096,655'Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure'2000 5,798,016'Apparatus for hot wall reactive ion etching using a dielectric or metallic liner with temperature control to achieve process stability'1998 5,637,237'Method for hot wall reactive ion etching using a dielectric or metallic liner with temperature control to achieve process stability'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2021Patents assigned to IBM (96)· patent assignee history

2000–2016Based in Yorktown Heights, NY, US· patent location history

2011–2016Patents assigned to ZHANG YING (36)· patent assignee history

2012–2014Patents assigned to CHENG KANGGUO (13)· patent assignee history

2012–2014Patents assigned to DORIS BRUCE B (13)· patent assignee history

2014–2017Based in Hsinchu, TW· patent location history

2015–2020Patents assigned to APPLIED MATERIALS INC (34)· patent assignee history

2015–2020Based in Santa Clara, CA, US· patent location history

2017–2020Based in Sunnyvale, CA, US· patent location history

2018Based in Redwood City, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	96	1997–2021
ZHANG YINGself	36	2011–2016
APPLIED MATERIALS INC	34	2015–2020
CHENG KANGGUO	13	2012–2014
DORIS BRUCE B	13	2012–2014

Locations

Location	Patents	Span
Yorktown Heights, New York, US	90	2000–2016
Santa Clara, California, US	43	2015–2020
Hsinchu, TW	10	2014–2017
Sunnyvale, California, US	5	2017–2020
Redwood City, California, US	2	2018