LexDanaLexDanabeta
Inventor

Michael E. Kounavis

Inventor
Portland, OR, US

Overview

85→
Patents
2008–2021
Patent span
Physics
Primary field (CPC G)

Patents· 85 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing32%
H04LTransmission of digital information, e.g. telegraphic communication23%
G06TImage data processing or generation, in general11%
G11CStatic stores11%
H03MCoding10%
G06KGraphical data reading4%
G06VImage or video recognition or understanding4%
H04WWireless communication networks2%
A63FCard, board, or roulette games0%
G10LSpeech analysis techniques or speech synthesis0%
PatentTitleYear
11,082,432Methods and apparatus to support reliable digital communications without integrity metadata202111,048,579Performing a cyclic redundancy checksum operation responsive to a user-level instruction202111,010,310Convolutional memory integrity202110,949,358Secure address translation services using message authentication codes and invalidation tracking202110,929,527Methods and arrangements for implicit integrity202110,891,255Heterogeneous multiprocessor including scalar and SIMD processors in a ratio defined by execution time and consumed die area202110,860,709Encoded inline capabilities202010,855,815Security-oriented compression202010,755,386Median filtering of images using directed search202010,757,227Security-oriented compression202010,672,401Speech and video dual mode gaussian mixture model scoring accelerator202010,585,809Convolutional memory integrity202010,581,590Flexible architecture and instruction for advanced encryption standard (AES)202010,554,386Flexible architecture and instruction for advanced encryption standard (AES)202010,540,198Technologies for memory replay prevention using compressive encryption202010,498,865Security-oriented compression201910,496,876Specular light shadow removal for image de-noising201910,379,938Performing a cyclic redundancy checksum operation responsive to a user-level instruction201910,346,318Multi-stage memory integrity method and apparatus201910,331,944Technologies for dynamic performance of image analysis201910,313,107Flexible architecture and instruction for advanced encryption standard (AES)201910,291,394Flexible architecture and instruction for advanced encryption standard (AES)201910,270,589Flexible architecture and instruction for advanced encryption standard (AES)201910,261,854Memory integrity violation analysis method and apparatus201910,262,397Image de-noising using an equalized gradient space201910,263,769Flexible architecture and instruction for advanced encryption standard (AES)201910,256,972Flexible architecture and instruction for advanced encryption standard (AES)201910,256,971Flexible architecture and instruction for advanced encryption standard (AES)201910,235,304Multi-crypto-color-group VM/enclave memory integrity method and apparatus201910,223,528Technologies for deterministic code flow integrity protection201910,187,201Flexible architecture and instruction for advanced encryption standard (AES)201910,181,945Flexible architecture and instruction for advanced encryption standard (AES)201910,171,231Flexible architecture and instruction for advanced encryption standard (AES)201910,171,232Flexible architecture and instruction for advanced encryption standard (AES)201910,164,769Flexible architecture and instruction for advanced encryption standard (AES)201810,158,478Flexible architecture and instruction for advanced encryption standard (AES)201810,148,426Method and apparatus for efficiently implementing the advanced encryption standard201810,074,205Machine creation of program with frame analysis method and apparatus201810,050,778Method and apparatus for efficiently implementing the advanced encryption standard20189,654,282'Flexible architecture and instruction for advanced encryption standard (AES)'20179,654,281'Flexible architecture and instruction for advanced encryption standard (AES)'20179,645,884'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20179,647,831'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,319'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,320'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,828'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,829'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,830'Flexible architecture and instruction for advanced encryption standard (AES)'20179,575,566'Technologies for robust two-dimensional gesture recognition'20179,558,389'Reliable fingertip and palm detection'20179,544,133'On-the-fly key generation for encryption and decryption'20179,536,136'Multi-layer skin detection and fused hand pose matching'20179,390,320'Performing hand gesture recognition using 2D image data'20169,116,684'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20158,923,510'Method and apparatus for efficiently implementing the advanced encryption standard'20148,861,847'System and method for adaptive skin tone detection'20148,856,627'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,804,951'Speeding up galois counter mode (GCM) computations'20148,793,559'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,775,911'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,775,912'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,775,910'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,769,385'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,769,386'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,713,416'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20148,538,015'Flexible architecture and instruction for advanced encryption standard (AES)'20138,533,246'Carry bucket-aware multiplication having bits with most significant bits set to zero'20138,478,809'Method and apparatus for multiplying polynomials with a prime number of terms'20138,442,217'Method of implementing one way hash functions and apparatus therefor'20138,413,024'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20138,340,280'Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations'20128,225,184'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20128,144,864'Method for speeding up the computations for characteristic 2 elliptic curve cryptographic systems'20127,991,152'Speeding up Galois Counter Mode (GCM) computations'20117,958,436'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'20117,886,214'Determining a message residue'20117,844,655'System, method and apparatus for multiplying large numbers in a single iteration using graphs'20107,826,612'System, method and apparatus for an incremental modular process including modular multiplication and modular eduction'20107,707,483'Technique for performing cyclic redundancy code error detection'20107,646,779'Hierarchical packet scheduler using hole-filling and multiple packet buffering'20107,590,930'Instructions for performing modulo-2 multiplication and bit reflection'20097,525,958'Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharing'20097,525,962'Reducing memory access bandwidth consumption in a hierarchical packet scheduler'20097,457,296'Method and apparatus for sorting packets in packet schedulers using a connected trie data structure'20087,408,932'Method and apparatus for two-stage packet classification using most specific filter matching and transport level sharing'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2021Patents assigned to INTEL CORP (85)· patent assignee history
2008–2014Based in Hillsboro, OR, US· patent location history
2008Based in New York, NY, US· patent location history
2012–2017Patents assigned to KOUNAVIS MICHAEL E (8)· patent assignee history
2012–2017Patents assigned to GUERON SHAY (7)· patent assignee history
2012–2013Patents assigned to KOUNAVIS MICHAEL (4)· patent assignee history
2012–2014Patents assigned to BERRY FRANK (3)· patent assignee history
2013–2021Based in Portland, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP852008–2021
KOUNAVIS MICHAEL Eself82012–2017
GUERON SHAY72012–2017
KOUNAVIS MICHAELself42012–2013
BERRY FRANK32012–2014
Locations
LocationPatentsSpan
Portland, OR, US642013–2021
Hillsboro, OR, US202008–2014
New York, New York, US12008