Inventor
Janusz K. Balicki
Inventor
San Jose, CA, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique78%
G11CStatic stores22%
PatentTitleYear
RE040011'System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly'20085,970,255'System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly'19995,953,537'Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device'19995,523,706'High speed, low power macrocell'19965,473,266'Programmable logic device having fast programmable logic array blocks and a central global interconnect array'19955,399,922'Macrocell comprised of two look-up tables and two flip-flops'19955,341,044'Flexible configuration logic array block for programmable logic devices'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2008Patents assigned to ALTERA CORP (7)· patent assignee history
1994–2008Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 7 | 1994–2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 7 | 1994–2008 |