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Inventor

Adam P. Matheny

Inventor
Beacon, NY, US

Overview

24→
Patents
2005–2021
Patent span
Physics
Primary field (CPC G)

Patents· 24 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
11,030,376Net routing for integrated circuit (IC) design202110,943,040Clock gating latch placement202110,885,243Logic partition reporting for integrated circuit design202110,878,152Single-bit latch optimization for integrated circuit (IC) design202010,831,953Logic partition identifiers for integrated circuit design202010,831,966Multi-fanout latch placement optimization for integrated circuit (IC) design202010,831,938Parallel power down processing of integrated circuit design202010,360,338Method for improving capacitance extraction performance by approximating the effect of distant shapes201910,354,041Process for improving capacitance extraction performance201910,331,840Resource aware method for optimizing wires for slew, slack, or noise201910,169,516Methods and computer program products for via capacitance extraction201910,169,526Incremental parasitic extraction for coupled timing and power optimization20199,934,341Simulation of modifications to microprocessor design20189,928,322'Simulation of modifications to microprocessor design'20189,886,541'Process for improving capacitance extraction performance'20189,858,383'Incremental parasitic extraction for coupled timing and power optimization'20189,785,735'Parallel incremental global routing'20179,256,705'Reducing repeater power'20169,223,918'Reducing repeater power'20158,032,851'Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit'20118,006,208'Reducing coupling between wires of an electronic circuit'20117,904,861'Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing'20117,581,201'System and method for sign-off timing closure of a VLSI chip'20096,958,545'Method for reducing wiring congestion in a VLSI chip design'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2021Patents assigned to IBM (23)· patent assignee history
2005–2019Based in Beacon, NY, US· patent location history
2015–2016Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2015Patents assigned to KARTSCHOKE PAUL D (1)· patent assignee history
2015Patents assigned to MATHENY ADAM P (1)· patent assignee history
2015Patents assigned to NEVES JOSE L (1)· patent assignee history
2017–2021Based in Hyde Park, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM232005–2021
GLOBALFOUNDRIES INC22015–2016
KARTSCHOKE PAUL D12015
MATHENY ADAM Pself12015
NEVES JOSE L12015
Locations
LocationPatentsSpan
Beacon, New York, US152005–2019
Hyde Park, New York, US92017–2021