Inventor
Nguyen Duc Bui
Inventor
San Jose, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
G01RMeasuring electric variables21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10DInorganic electric semiconductor devices12%
H10BElectronic memory devices9%
B24BMachines, devices, or processes for grinding or polishing3%
G06FElectric digital data processing3%
G11CStatic stores3%
H01LSemiconductor devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
11,003,697Cluster computing system and method for automatically generating extraction patterns from operational logs202110,217,521Multi-time programmable non-volatile memory cell20196,703,305'Semiconductor device having metallized interconnect structure and method of fabrication'20046,700,154'EEPROM cell with trench coupling capacitor'20046,472,233'MOSFET test structure for capacitance-voltage measurements'20026,413,820'Method of forming a composite interpoly gate dielectric'20026,329,831'Method and apparatus for reliability testing of integrated circuit structures and devices'20016,320,391'Interconnection device for low and high current stress electromigration and correlation study'20016,163,049'Method of forming a composite interpoly gate dielectric'20006,100,101'Sensitive technique for metal-void detection'20006,063,662'Methods for forming a control gate apparatus in non-volatile memory semiconductor devices'20006,005,409'Detection of process-induced damage on transistors in real time'19995,966,024'Sensitive method of evaluating process induced damage in MOSFETs using a differential amplifier operational principle'19995,808,361'Intergrated circuit interconnect via structure having low resistance'19985,786,705'Method for evaluating the effect of a barrier layer on electromigration for plug and non-plug interconnect systems'19985,726,458'Hot carrier injection test structure and technique for statistical evaluation'19985,712,510'Reduced electromigration interconnection line'19985,689,139'Enhanced electromigration lifetime of metal interconnection lines'19975,650,651'Plasma damage reduction device for sub-half micron technology'19975,612,627'Method for evaluating the effect of a barrier layer on electromigration for plug and non-plug interconnect systems'19975,598,009'Hot carrier injection test structure and testing technique for statistical evaluation'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2002Patents assigned to ADVANCED MICRO DEVICES INC (17)· patent assignee history
1997–2019Based in San Jose, CA, US· patent location history
2004–2019Patents assigned to LATTICE SEMICONDUCTOR CORP (3)· patent assignee history
2021Patents assigned to HO CHI MINH CITY UNIV OF TECHNOLOGY HUTECH (1)· patent assignee history
2021Based in Ho Chi Minh, VN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 17 | 1997–2002 |
| LATTICE SEMICONDUCTOR CORP | 3 | 2004–2019 |
| HO CHI MINH CITY UNIV OF TECHNOLOGY HUTECH | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 20 | 1997–2019 |
| Ho Chi Minh, VN | 1 | 2021 |