Inventor
WEI-CHENG LIN
Inventor
TW
Overview
Patents· 110 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices24%
H01LSemiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
G06FElectric digital data processing10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
B82YSpecific uses or applications of nanostructures3%
H03KPulse technique3%
Y02PClimate change mitigation technologies in the production or processing of goods2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H04MTelephonic communication1%
PatentTitleYear
12,592,522Connector assembly202612,588,488Integrated circuit structure202612,581,745Integrated circuit and system for fabricating the same202612,581,939Contact structure manufacturing method202612,564,043Manufacturing method for semiconductor device202612,538,543Methods of manufacture of semiconductor devices202612,490,498Semiconductor device and manufacturing method thereof202512,476,197Semiconductor device202512,462,086Integrated circuit having hybrid sheet structure202512,456,679Backside conductive segments cover a first active region and define an opening above a second active region202512,457,801APR placement for hybrid sheet cells202512,456,678Methods for generating a circuit with high density routing layout202512,431,428Integrated circuits and methods for power delivery202512,417,941Isolation structures in semiconductor devices202512,414,344Semiconductor device having active regions of different dimensions and method of manufacturing the same202512,388,009Semiconductor device including structure connecting frontside and backside metal and method of manufacturing the same202512,388,016Deep lines and shallow lines in signal conducting paths202512,388,428Integrated circuit having latch with transistors of different gate widths202512,388,013Three dimensional integrated circuit with monolithic inter-tier vias (MIV)202512,367,332Mixed poly pitch design solution for power trim202512,339,321Semiconductor device and method of failure analysis for semiconductor device202512,341,098Metal patterning for internal cell routing202512,324,245Layout architecture for a cell202512,317,589Power rail and signal conducting line arrangement202512,314,650Integrated circuit device and manufacturing method of the same202512,315,804Back side signal routing in a circuit with a relay cell202512,307,183Variable width nano-sheet field-effect transistor cell structure202512,300,608Method of manufacturing semiconductor device202512,299,372Mixed poly pitch design solution for power trim202512,288,785Layout designs of integrated circuits having backside routing tracks202512,283,546Integrated circuit and method for forming the same202512,278,238Semiconductor structure and method of forming the same202512,270,847Antenna test system202512,264,166Asymmetric fused aromatic ring derivative containing sulfonyl group, hydrogen production device and optoelectronic component202512,261,113Middle-end-of-line strap for standard cell202512,261,116Backside signal routing202512,237,334Semiconductor structure202512,225,973Method for manufacturing recycled carbon fiber underlay and recycled carbon fiber arch insole with recycled carbon fiber underlay202512,230,572Backside signal interconnection202512,218,050Manufacturing method for semiconductor device202512,218,141Hybrid fin field-effect transistor cell structures and related methods202512,148,700Semiconductor device, and associated method and system202412,142,611Semiconductor structure for reducing stray capacitance and method of forming the same202412,131,998Integrated circuit, system and method of forming same202412,113,014Integrated circuit including supervia and method of making202412,107,045Middle-end-of-line strap for standard cell202412,095,472Transceiver circuit and control method of frequency synthesizer202412,094,777Method for manufacturing semiconductor device202412,086,524Semiconductor device having more similar cell densities in alternating rows202412,079,559IC device layout method202412,068,305Multiple fin height integrated circuit202412,067,341Semiconductor structure, device, and method202412,034,076Semiconductor device integrating backside power grid and related integrated circuit and fabrication method202412,021,021Integrated circuit structure202412,003,242Integrated circuit having latch with transistors of different gate widths202411,990,477Hybrid fin field-effect transistor cell structures and related methods202411,984,443Power distribution network202411,973,117Semiconductor device202411,967,596Power rail and signal conducting line arrangement202411,935,825Contact structure, method, layout, and system202411,935,830Integrated circuit with frontside and backside conductive layers and exposed backside substrate202411,923,301Method of manufacturing semiconductor device202411,923,297Apparatus and methods for generating a circuit with high density routing layout202411,923,369Integrated circuit, system and method of forming the same202411,916,070Semiconductor structure with nanosheets202411,916,077Method for routing local interconnect structure at same level as reference metal line202411,916,074Double rule integrated circuit layouts for a dual transmission gate202411,908,852Layout designs of integrated circuits having backside routing tracks202411,893,333Hybrid sheet layout, method, system, and structure202411,894,375Semiconductor structure and method of forming the same202411,862,561Semiconductor devices with backside routing and method of forming same202411,854,786Deep lines and shallow lines in signal conducting paths202311,842,137Integrated circuit and method of manufacturing same202311,842,967Semiconductor devices with backside power distribution network and frontside through silicon via202311,797,746Method of forming semiconductor device having more similar cell densities in alternating rows202311,783,109IC device manufacturing method202311,769,723Three dimensional integrated circuit with monolithic inter-tier vias (MIV)202311,756,876Semiconductor devices having power rails and signal tracks arranged in different layer202311,755,812Power structure with power pick-up cell connecting to buried power rail202311,755,808Mixed poly pitch design solution for power trim202311,741,288Routing-resource-improving method of generating layout diagram, system for same and semiconductor device202311,735,517Integrated circuit including super via and method of making202311,728,269Semiconductor device, and associated method and system202311,720,737Semiconductor structure, device, and method202311,688,691Method of making standard cells having via rail and deep via structures202311,658,119Backside signal interconnection202311,637,066Integrated circuit and method for forming the same202311,626,369Integrated circuit, system and method of forming same202311,569,167Method of manufacturing semiconductor device202311,569,166Semiconductor device and manufacturing method thereof202311,538,754Random cut patterning202211,532,482High-density semiconductor device202211,532,751Metal rail conductors for non-planar semiconductor devices202211,532,553Middle-end-of-line strap for standard cell202211,515,197Semiconductor device and method of forming the semiconductor device202211,476,250Double rule integrated circuit layouts for a dual transmission gate202211,444,073Power distribution network202211,429,774Variable width nano-sheet field-effect transistor cell structure202211,409,937Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same202211,374,005Semiconductor structure and method of forming the same202211,362,050Multi-chip packing structure employing millimeter wave202211,356,246Data analysis system and data analysis method202211,355,487Layout designs of integrated circuits having backside routing tracks202211,328,957Semiconductor device and manufacturing method thereof202211,309,247Semiconductor device, and associated method and system202211,270,936Integrated circuit including supervia and method of making202211,232,248Routing-resource-improving method of generating layout diagram and system for same202211,217,528Semiconductor structure having buried power rail disposed between two fins and method of making the same202211,158,580Semiconductor devices with backside power distribution network and frontside through silicon via202111,159,164Integrated circuit and method of manufacturing the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (103)· patent assignee history
2021–2026Based in TW· patent location history
2022Patents assigned to KEYCORE TECH CORP (1)· patent assignee history
2025Patents assigned to DR FOOT TECH CO LTD (1)· patent assignee history
2025Patents assigned to LIN WEI CHENG (1)· patent assignee history
2026Patents assigned to MOLEX LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 103 | 2021–2026 |
| DR FOOT TECH CO LTD | 1 | 2025 |
| KEYCORE TECH CORP | 1 | 2022 |
| LIN WEI CHENGself | 1 | 2025 |
| MOLEX LLC | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 110 | 2021–2026 |