Inventor
Edward T. Grochowski
Inventor
San Jose, CA, US
Overview
Patents· 102 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing77%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
H03KPulse technique2%
G01RMeasuring electric variables2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10DInorganic electric semiconductor devices2%
G06TImage data processing or generation, in general1%
H03HImpedance networks, e.g. resonant circuits1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
11,113,053Data element comparison processors, methods, systems, and instructions202111,093,277Systems, methods, and apparatuses for heterogeneous computing202111,048,508Interruptible and restartable matrix multiplication instructions, processors, methods, and systems202110,891,255Heterogeneous multiprocessor including scalar and SIMD processors in a ratio defined by execution time and consumed die area202110,853,065Systems, apparatuses, and methods for chained fused multiply add202010,795,680Vector friendly instruction format and execution thereof202010,775,873Performing power management in a multicore processor202010,635,438Method and system to provide user-level multithreading202010,628,153Method and system to provide user-level multithreading202010,613,858Method and system to provide user-level multithreading202010,585,667Method and system to provide user-level multithreading202010,579,378Instructions for manipulating a multi-bit predicate register for predicating instruction sequences202010,489,063Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication201910,452,403Mechanism for instruction set based thread execution on a plurality of instruction sequencers201910,445,244Method, system, and apparatus for page sizing extension201910,445,245Method, system, and apparatus for page sizing extension201910,423,411Data element comparison processors, methods, systems, and instructions201910,282,296Zeroing a cache line201910,275,243Interruptible and restartable matrix multiplication instructions, processors, methods, and systems201910,261,904Memory sequencing with coherent and non-coherent sub-systems201910,234,930Performing power management in a multicore processor201910,146,535Systems, apparatuses, and methods for chained fused multiply add20189,990,206Mechanism for instruction set based thread execution of a plurality of instruction sequencers20189,977,674Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction20189,934,155Method, system, and apparatus for page sizing extension20189,934,032Processors, methods, and systems to implement partial register accesses with masked full register accesses20189,898,286'Packed finite impulse response (FIR) filter processors, methods, systems, and instructions'20189,875,185Memory sequencing with coherent and non-coherent sub-systems20189,875,213Methods, apparatus, instructions and logic to provide vector packed histogram functionality20189,785,436'Apparatus and method for efficient gather and scatter operations'20179,513,917'Vector friendly instruction format and execution thereof'20169,477,467'Processors, methods, and systems to implement partial register accesses with masked full register accesses'20169,465,670'Generational thread scheduler using reservations for fair scheduling'20169,442,721'Method and system to provide user-level multithreading'20169,367,314'Converting conditional short forward branches to computationally equivalent predicated instructions'20169,189,230'Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution'20159,170,955'Providing extended cache replacement state information'20158,601,242'Adaptive optimized compare-exchange operation'20138,533,436'Adaptively handling remote atomic execution based upon contention prediction'20138,125,246'Method and apparatus for late timing transition detection'20127,742,910'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20107,622,961'Method and apparatus for late timing transition detection'20097,516,312'Presbyopic branch target prefetch method and apparatus'20097,480,838'Method, system and apparatus for detecting and recovering from timing errors'20097,437,581'Method and apparatus for varying energy per instruction according to the amount of available parallelism'20087,395,304'Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic'20087,380,111'Out-of-order processing with predicate prediction and validation with correct RMW partial write new predicate register values'20087,340,643'Replay mechanism for correcting soft errors'20087,315,920'Circuit and method for protecting vector tags in high performance microprocessors'20087,281,140'Digital throttle for multiple operating points'20077,236,920'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20077,111,154'Method and apparatus for NOP folding'20067,085,919'Predicate prediction based on a predicated predicate value'20067,062,639'Method and apparatus for performing predicate prediction'20067,035,785'Mechanism for estimating and controlling di/dt-induced power supply voltage variations'20067,020,590'Simulation of di/dt-induced power supply voltage variation'20066,954,848'Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately'20056,938,126'Cache-line reuse-buffer'20056,931,559'Multiple mode power throttle mechanism'20056,928,645'Software-based speculative pre-computation and multithreading'20056,904,502'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors'20056,857,051'Method and apparatus for maintaining cache coherence in a computer system'20056,839,814'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors'20056,826,588'Method and apparatus for a fast comparison in redundant form arithmetic'20046,813,628'Method and apparatus for performing equality comparison in redundant form arithmetic'20046,775,746'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors'20046,763,368'Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic'20046,757,814'Method and apparatus for performing predicate prediction'20046,754,689'Method and apparatus for performing subtraction in redundant form arithmetic'20046,732,260'Presbyopic branch target prefetch method and apparatus'20046,678,815'Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end'20046,675,266'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors'20046,636,976'Mechanism to control di/dt for a microprocessor'20036,625,756'Replay mechanism for soft error recovery'20036,615,366'Microprocessor with dual execution core operable in high reliability mode'20036,564,332'Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet'20036,564,328'Microprocessor with digital power throttle'20036,367,023'Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system'20026,367,004'Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared'20026,353,883'Method and apparatus for performing predicate prediction'20026,205,542'Processor pipeline including replay'20016,115,807'Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued'20006,088,790'Using a table to track and locate the latest copy of an operand'20006,076,153'Processor pipeline including partial replay'20006,047,370'Control of processor pipeline movement through replay queue and pointer backup'20006,035,389'Scheduling instructions with different latencies'20006,021,500'Processor with sleep and deep sleep modes'20005,696,935'Multiported cache and systems'19975,692,167'Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor'19975,606,676'Branch prediction and resolution apparatus for a superscalar computer processor'19975,586,276'End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions'19965,581,718'Method and apparatus for selecting instructions for simultaneous execution'19965,555,423'Multi-mode microprocessor having a pin for resetting its register without purging its cache'19965,535,347'Rotators in machine instruction length calculation'19965,475,824'Microprocessor with apparatus for parallel execution of instructions'19955,450,605'Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions'19955,442,756'Branch prediction and resolution apparatus for a superscalar computer processor'19955,416,913'Method and apparatus for dependency checking in a multi-pipelined microprocessor'19955,414,824'Apparatus and method for accessing a split line in a high speed cache'19955,255,378'Method of transferring burst data in a microprocessor'19935,131,083'Method of transferring burst data in a microprocessor'19924,985,640'Apparatus for generating computer clock pulses'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2021Patents assigned to INTEL CORP (102)· patent assignee history
1991–2021Based in San Jose, CA, US· patent location history
2012–2013Patents assigned to GROCHOWSKI EDWARD (2)· patent assignee history
2013–2018Patents assigned to GROCHOWSKI EDWARD T (4)· patent assignee history
2013Patents assigned to FORSYTH ANDREW THOMAS (2)· patent assignee history
2013Patents assigned to FRYMAN JOSHUA B (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 102 | 1991–2021 |
| GROCHOWSKI EDWARD Tself | 4 | 2013–2018 |
| FORSYTH ANDREW THOMAS | 2 | 2013 |
| FRYMAN JOSHUA B | 2 | 2013 |
| GROCHOWSKI EDWARDself | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 102 | 1991–2021 |