Inventor
Prashant Shamarao
Inventor
Cupertino, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing40%
H03KPulse technique15%
G09GArrangements or circuits for control of indicating devices using static means to present variable information13%
H04LTransmission of digital information, e.g. telegraphic communication10%
H03MCoding5%
H04NPictorial communication, e.g. television5%
G01RMeasuring electric variables3%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
G05FSystems for regulating electric or magnetic variables3%
G11CStatic stores3%
PatentTitleYear
11,120,732Device and method for driving display in response to image data202110,614,747Device and method for driving display panel in response to image data202010,394,391System and method for reducing display artifacts201910,375,349Branch device bandwidth management for video streams201910,367,662Method and apparatus for novel adaptive equalization technique for serializer/deserializer links201910,063,397Method and apparatus for novel adaptive equalization technique for serializer/deserializer links20189,983,721Optimizing pixel settling in an integrated display and capacitive sensing device20189,898,150'Source driver uplink as indicator of downlink status'20189,875,211Signal conditioner for high-speed data communications20189,836,173Optimizing pixel settling in an integrated display and capacitive sensing device20179,509,308'Supply-modulation cross domain data interface'20169,323,698'System and method for transmitting USB data over a DisplayPort transmission link'20168,686,759'Bi-directional channel amplifier'20148,432,408'Data rate buffering in display port links'20137,911,261'Substrate bias circuit and method for integrated circuit device'20117,555,668'DRAM interface circuits that support fast deskew calibration and methods of operating same'20097,548,105'Method and apparatus for source synchronous testing'20097,447,812'Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files'20087,134,034'Data paths with receiver timing fixable to a downstream stage and methods of operation thereof'20066,907,479'Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same'20056,894,529'Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control'20056,356,102'Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals'20026,242,942'Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics'20016,119,141'Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU'20006,091,260'Integrated circuit output buffers having low propagation delay and improved noise characteristics'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2019Patents assigned to INTEGRATED DEVICE TECH (12)· patent assignee history
2000–2002Based in Atlanta, GA, US· patent location history
2005–2009Based in Alpharetta, GA, US· patent location history
2011–2016Based in Duluth, GA, US· patent location history
2013–2021Patents assigned to SYNAPTICS INC (12)· patent assignee history
2013–2018Patents assigned to SHAMARAO PRASHANT (4)· patent assignee history
2014Patents assigned to BISHOP ROBERT (1)· patent assignee history
2016–2021Based in Cupertino, CA, US· patent location history
2018Patents assigned to CHEN YONGGANG (1)· patent assignee history
2018–2019Based in Johns Creek, GA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 12 | 2000–2019 |
| SYNAPTICS INC | 12 | 2013–2021 |
| SHAMARAO PRASHANTself | 4 | 2013–2018 |
| BISHOP ROBERT | 1 | 2014 |
| CHEN YONGGANG | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 9 | 2016–2021 |
| Alpharetta, Georgia, US | 5 | 2005–2009 |
| Duluth, Georgia, US | 4 | 2011–2016 |
| Atlanta, Georgia, US | 3 | 2000–2002 |
| Johns Creek, Georgia, US | 2 | 2018–2019 |