Inventor
Dharmaray Nedalgi
Inventor
Bangalore, IN
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique33%
H02HEmergency protective circuit arrangements14%
G06FElectric digital data processing10%
H01LSemiconductor devices10%
H04BTransmission10%
H04LTransmission of digital information, e.g. telegraphic communication10%
H10BElectronic memory devices5%
H10DInorganic electric semiconductor devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
PatentTitleYear
10,938,200Back power protection circuit202110,693,450Apparatus and method for over-voltage protection202010,128,248Aging tolerant apparatus20189,601,916'Back power protection circuit'20178,629,692'State definition and retention circuit'20148,330,491'Electronic device with a high voltage tolerant unit'20128,283,947'High voltage tolerant bus holder circuit and method of operating the circuit'20127,969,191'Low-swing CMOS input circuit'20117,741,874'Electronic circuit'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2014Patents assigned to NXP BV (3)· patent assignee history
2010–2021Based in Bangalore, IN· patent location history
2011–2012Patents assigned to SYNOPSYS INC (2)· patent assignee history
2012–2014Patents assigned to NEDALGI DHARMARAY M (3)· patent assignee history
2012–2014Patents assigned to UBARADKA JAYARAMA (2)· patent assignee history
2017–2021Patents assigned to INTEL CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 3 | 2017–2021 |
| NEDALGI DHARMARAY Mself | 3 | 2012–2014 |
| NXP BV | 3 | 2010–2014 |
| SYNOPSYS INC | 2 | 2011–2012 |
| UBARADKA JAYARAMA | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 9 | 2010–2021 |