Inventor
Tony L. Werner
Inventor
Los Altos, CA, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing62%
G06NComputing arrangements based on specific computational models23%
G06TImage data processing or generation, in general4%
G06VImage or video recognition or understanding4%
H04LTransmission of digital information, e.g. telegraphic communication4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
10,949,496Dimension shuffling using matrix processors202110,896,039Programmable matrix processing engine202110,761,757Apparatus and method for coherent, accelerated conversion between data representations202010,620,951Matrix multiplication acceleration of sparse matrices using column folding and squeezing202010,482,155Winograd algorithm on a matrix processing architecture201910,228,937Programmable matrix processing engine201910,198,401Max pooling in a matrix processing architecture20199,886,377'Pipelined convolutional operations for processing clusters'20189,886,418'Matrix operands for linear algebra operations'20187,408,937'Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms'20087,159,102'Branch control memory'20076,772,325'Processor architecture and operation for exploiting improved branch control instruction'20046,449,712'Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions'20026,397,296'Two-level instruction cache for embedded processors'20026,393,523'Mechanism for invalidating instruction cache blocks in a pipeline processor'20026,389,531'Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency'20026,374,348'Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2004Patents assigned to HITACHI LTD (6)· patent assignee history
2002–2007Based in Santa Clara, CA, US· patent location history
2002Based in San Jose, CA, US· patent location history
2007Patents assigned to RENESAS TECH CORP (1)· patent assignee history
2008Patents assigned to CISCO TECH INC (1)· patent assignee history
2008–2021Based in Los Altos, CA, US· patent location history
2018–2021Patents assigned to INTEL CORP (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 9 | 2018–2021 |
| HITACHI LTD | 6 | 2002–2004 |
| CISCO TECH INC | 1 | 2008 |
| RENESAS TECH CORP | 1 | 2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 10 | 2008–2021 |
| Santa Clara, California, US | 6 | 2002–2007 |
| San Jose, California, US | 1 | 2002 |