Inventor
GEORG SEIDEMANN
Inventor
DE
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H10DInorganic electric semiconductor devices9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H05KPrinted circuits3%
H01QAntennas, i.e. radio aerials2%
B82YSpecific uses or applications of nanostructures1%
H01FMagnets1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
12,581,929Semiconductor devices and methods for forming a semiconductor device202612,568,663Threshold voltage tuning for nanoribbon-based transistors202612,538,797Substrate for improved heat dissipation and method202612,525,562Assembly of 2XD module using high density interconnect bridges202612,476,176Glass core substrate printed circuit board for warpage reduction202512,439,616Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors202512,431,424Buried power rails integrated with decoupling capacitance202512,406,925Bare-die smart bridge connected with copper pillars for system-in-package apparatus202512,394,726Method to implement wafer-level chip-scale packages with grounded conformal shield202512,382,712Semiconductor dies and devices with frontside and backside coils for inductive coupling202512,374,625Microelectronic assemblies having topside power delivery structures202512,347,796Semiconductor dies and devices with a coil for inductive coupling202512,341,096Bare-die smart bridge connected with copper pillars for system-in-package apparatus202512,249,553Thermal contacts at periphery of integrated circuit packages202512,243,856Fan out packaging pop mechanical attach method202512,243,828Microelectronic assemblies having topside power delivery structures202512,211,796Microelectronic assemblies having topside power delivery structures202512,191,571Antenna with graded dielectirc and method of making the same202512,125,815Assembly of 2XD module using high density interconnect bridges202412,080,655Method to implement wafer-level chip-scale packages with grounded conformal shield202412,057,411Stress relief die implementation202411,955,462Package stacking using chip to wafer bonding202411,877,403Printed wiring-board islands for connecting chip packages and methods of assembling same202411,764,187Semiconductor packages, and methods for forming semiconductor packages202311,735,570Fan out packaging pop mechanical attach method202311,469,213Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics202211,456,116Magnetic coils in locally thinned silicon bridges and methods of assembling same202211,424,209Wafer level package structure with internal conductive layer202211,374,323Patch antennas stitched to systems in packages and methods of assembling same202211,270,941Bare-die smart bridge connected with copper pillars for system-in-package apparatus202211,239,199Package stacking using chip to wafer bonding202211,177,220Vertical and lateral interconnects between dies202111,145,577Lead frame with angular deflections and wrapped printed wiring boards for system-in-package apparatus2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (33)· patent assignee history
2021–2025Patents assigned to INTEL IP CORP (2)· patent assignee history
2021–2026Based in DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 33 | 2021–2026 |
| INTEL IP CORP | 2 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| DE | 33 | 2021–2026 |