Inventor
Victor Zyuban
Inventor
Yorktown Heights, NY, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing40%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use21%
H03KPulse technique15%
G11CStatic stores5%
H02JElectric power networks5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
G01RMeasuring electric variables2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
G05BControl or regulating systems in general1%
PatentTitleYear
11,121,711Method for multiplexing between power supply signals for voltage limited circuits202111,005,459Efficient retention flop utilizing different voltage domain202110,908,663Power switch multiplexer with configurable overlap202110,763,859Method for multiplexing between power supply signals for voltage limited circuits202010,599,207Management of core power state transition in a microprocessor202010,523,194Low leakage power switch201910,483,974Method for multiplexing between power supply signals for voltage limited circuits201910,187,045Balancing delay associated with dual-edge trigger clock gaters201910,084,450Method for multiplexing between power supply signals for voltage limited circuits20189,971,393Dynamic workload frequency optimization20189,952,651Deterministic current based frequency optimization of processor chip20189,933,836Management of core power state transition in a microprocessor20189,929,723'Flip flop using dual inverter feedback'20189,871,507'Generating an overdrive voltage for power switch circuitry'20189,778,726'Deterministic current based frequency optimization of processor chip'20179,712,141'Modulation of power supply voltage for varying propagation delay'20179,660,620'Dual-edge trigger clock gater'20179,568,982'Management of core power state transition in a microprocessor'20179,477,568'Managing interconnect electromigration effects'20169,471,136'Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating'20169,423,865'Accelerating microprocessor core wake up via charge from capacitance tank without introducing noise on power grid of running microprocessor cores'20169,424,381'Contributor-based power modeling of microprocessor components'20169,389,674'Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating'20169,323,302'Rotating voltage control'20169,298,253'Accelerating the microprocessor core wakeup by predictively executing a subset of the power-up sequence'20169,292,079'Accelerating the microprocessor core wakeup by predictively executing a subset of the power-up sequence'20168,796,047'Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip'20148,679,861'Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip'20148,589,662'Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals'20138,458,501'Measuring data switching activity in a microprocessor'20138,151,092'Control signal memoization in a multiple instruction issue microprocessor'20128,108,714'Method and system for soft error recovery during processor execution'20127,930,578'Method and system of peak power enforcement via autonomous token-based control and management'20117,774,654'Method and apparatus for preventing soft error accumulation in register arrays'20107,496,733'System and method of execution of register pointer instructions ahead of instruction issues'20097,493,523'Method and apparatus for preventing soft error accumulation in register arrays'20097,489,161'Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms'20097,486,107'Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms'20097,472,038'Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques'20087,461,209'Transient cache storage with discard function for disposable data'20087,447,923'Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power'20087,391,233'Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms'20087,391,232'Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms'20087,386,851'System and method for implementing dynamic lifetime reliability extension for microprocessor architectures'20087,325,124'System and method of execution of register pointer instructions ahead of instruction issue'20087,076,681'Processor with demand-driven clock throttling power reduction'20067,051,186'Selective bypassing of a multi-port register file'20066,990,509'Ultra low power adder with sum synchronization'20066,915,411'SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to IBM (35)· patent assignee history
2005–2020Based in Yorktown Heights, NY, US· patent location history
2006Based in Peekskill, NY, US· patent location history
2012–2014Patents assigned to RIVERS JUDE A (4)· patent assignee history
2012–2014Patents assigned to BOSE PRADIP (3)· patent assignee history
2016Patents assigned to GLOBALFOUNDRIES INC (4)· patent assignee history
2017–2021Patents assigned to APPLE INC (12)· patent assignee history
2017–2021Based in Sunnyvale, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 35 | 2005–2020 |
| APPLE INC | 12 | 2017–2021 |
| GLOBALFOUNDRIES INC | 4 | 2016 |
| RIVERS JUDE A | 4 | 2012–2014 |
| BOSE PRADIP | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yorktown Heights, New York, US | 36 | 2005–2020 |
| Sunnyvale, California, US | 12 | 2017–2021 |
| Peekskill, New York, US | 1 | 2006 |