Inventor
Yu-Ku Lin
Inventor
Hsinchu, TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices14%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation11%
B24BMachines, devices, or processes for grinding or polishing9%
C25DProcesses for the electrolytic or electrophoretic production of coatings6%
H10DInorganic electric semiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B08BCleaning in general2%
C25FProcesses for the electrolytic removal of materials from objects2%
PatentTitleYear
10,867,889Method of manufacturing semiconductor structure202010,818,716Image sensor device and fabricating method thereof202010,367,021Image sensor device and fabricating method thereof201910,074,594Semiconductor structure and manufacturing method thereof20189,991,204Through via structure for step coverage improvement20189,859,124'Method of manufacturing semiconductor device with recess'20189,711,454'Through via structure for step coverage improvement'20179,601,535'Semiconducator image sensor having color filters formed over a high-K dielectric grid'20179,419,155'Sensing product and method of making'20168,815,630'Back side illumination (BSI) sensors, manufacturing methods thereof, and semiconductor device manufacturing methods'20148,642,439'Semiconductor device and method of formation'20148,435,893'Semiconductor device and method of formation'20137,955,993'Oxygen plasma reduction to eliminate precursor overflow in BPTEOS film deposition'20117,417,321'Via structure and process for forming the same'20087,368,379'Multi-layer interconnect structure for semiconductor devices'20087,312,149'Copper plating of semiconductor devices using single intermediate low power immersion step'20077,304,728'Test device and method for laser alignment calibration'20077,128,821'Electropolishing method for removing particles from wafer surface'20067,071,100'Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process'20066,863,491'Catch-pin water support for process chamber'20056,769,959'Method and system for slurry usage reduction in chemical mechanical polishing'20046,695,921'Hoop support for semiconductor wafer'20046,682,605'Apparatus and method for removing coating layers from alignment marks'20046,626,741'Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing'20036,551,927'CoSix process to improve junction leakage'20036,531,382'Use of a capping layer to reduce particle evolution during sputter pre-clean procedures'20036,514,673'Rule to determine CMP polish time'20036,372,645'Methods to reduce metal bridges and line shorts in integrated circuits'20026,352,924'Rework method for wafers that trigger WCVD backside alarm'20026,248,002'Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish'20016,232,043'Rule to determine CMP polish time'20016,099,662'Process for cleaning a semiconductor substrate after chemical-mechanical polishing'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (22)· patent assignee history
2000–2008Based in Hsinchu, TW· patent location history
2006–2016Patents assigned to LIN YU-KU (3)· patent assignee history
2006–2016Patents assigned to WANG YING-LANG (3)· patent assignee history
2008Based in Hsin Chu, TW· patent location history
2011–2020Based in Tainan, TW· patent location history
2013–2016Patents assigned to CHANG SHIH-CHIEH (2)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 22 | 2000–2014 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 9 | 2016–2020 |
| LIN YU-KUself | 3 | 2006–2016 |
| WANG YING-LANG | 3 | 2006–2016 |
| CHANG SHIH-CHIEH | 2 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 18 | 2000–2008 |
| Tainan, TW | 13 | 2011–2020 |
| Hsin Chu, TW | 1 | 2008 |