Inventor
Alexander H. Owens
Inventor
Los Gatos, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10BElectronic memory devices6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
B67DDispensing, delivering or transferring liquids, not otherwise provided for2%
F17CVessels for containing or storing compressed, liquefied or solidified gases2%
H01LSemiconductor devices2%
PatentTitleYear
10,995,912Fuel transfer adapters20218,765,534'Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus'20148,395,216'Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus'20137,795,126'Electrical die contact structure and fabrication method'20107,340,181'Electrical die contact structure and fabrication method'20086,946,706'LDMOS transistor structure for improving hot carrier reliability'20056,586,302'Method of using trenching techniques to make a transistor with a floating gate'20036,579,777'Method of forming local oxidation with sloped silicon recess'20035,998,280'Modified recessed locos isolation process for deep sub-micron device processes'19995,661,069'Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space'19975,621,616'High density CMOS integrated circuit with heat transfer structure for improved cooling'19975,612,552'Multilevel gate array integrated circuit structure with perpendicular access to all active device regions'19975,561,319'Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof'19965,516,731'High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance'19965,220,192'Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof'19935,091,321'Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit'19925,045,492'Method of making integrated circuit with high current transistor and CMOS transistors'19914,914,051'Method for making a vertical power DMOS transistor with small signal bipolar transistors'19904,774,202'Memory device with interconnected polysilicon layers and method for making'19884,706,102'Memory device with interconnected polysilicon layers and method for making'19874,646,425'Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer'19874,598,460'Method of making a CMOS EPROM with independently selectable thresholds'19864,590,665'Method for double doping sources and drains in an EPROM'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–1987Patents assigned to SOLID STATE SCIENT (3)· patent assignee history
1986–1991Based in Pennington, NJ, US· patent location history
1987–1990Patents assigned to SPRAGUE ELECTRIC CO (3)· patent assignee history
1991–1992Patents assigned to ALLEGRO MICROSYSTEMS INC (2)· patent assignee history
1992–1996Based in Santa Clara, CA, US· patent location history
1996–2003Patents assigned to LSI LOGIC CORP (6)· patent assignee history
1996–2014Based in Los Gatos, CA, US· patent location history
1999–2014Patents assigned to NAT SEMICONDUCTOR CORP (7)· patent assignee history
2021Based in Wicklow, IE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 7 | 1999–2014 |
| LSI LOGIC CORP | 6 | 1996–2003 |
| SOLID STATE SCIENT | 3 | 1986–1987 |
| SPRAGUE ELECTRIC CO | 3 | 1987–1990 |
| ALLEGRO MICROSYSTEMS INC | 2 | 1991–1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 12 | 1996–2014 |
| Pennington, New Jersey, US | 7 | 1986–1991 |
| Santa Clara, California, US | 3 | 1992–1996 |
| Wicklow, IE | 1 | 2021 |