Inventor
DECHAO GUO
Inventor
US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices25%
B82YSpecific uses or applications of nanostructures13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10BElectronic memory devices3%
G11CStatic stores2%
G06FElectric digital data processing1%
G06KGraphical data reading1%
G06NComputing arrangements based on specific computational models1%
PatentTitleYear
12,568,661Self-aligned backside trench epitaxy for low contact resistivity202612,550,359Forming a sacrificial liner for dual channel devices202612,471,355Non-overlapping gate conductors for GAA transistors202512,457,762Cross bar vertical FETs202512,433,020Multi-VT solution for replacement metal gate bonded stacked FET202512,374,615Electronic devices with a low dielectric constant202512,363,990Upper and lower gate configurations of monolithic stacked FinFET transistors202512,336,294Gate-cut and separation techniques for enabling independent gate control of stacked transistors202512,317,537Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure202512,278,184Vertically-stacked field effect transistor cell202512,278,237Stacked FETS with non-shared work function metals202512,272,648Semiconductor device having a backside power rail202512,268,031Backside power rails and power distribution network for density scaling202512,176,348Self-aligned hybrid substrate stacked gate-all-around transistors202412,176,250Metal gate boundary for transistor scaling202412,148,833Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer202412,142,656Staggered stacked semiconductor devices202412,107,168Independent gate length tunability for stacked transistors202412,087,691Semiconductor structures with backside gate contacts202412,034,005Self-aligned metal gate with poly silicide for vertical transport field-effect transistors202411,984,401Stacked FET integration with BSPDN202411,908,743Planar devices with consistent base dielectric202411,895,818Stacked FET SRAM202411,894,423Contact resistance reduction in nanosheet device structure202411,894,462Forming a sacrificial liner for dual channel devices202411,869,893Stacked field effect transistor with wrap-around contacts202411,817,501Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer202311,757,012Source and drain contact cut last process to enable wrap-around-contact202311,749,744Fin structure for vertical transport field effect transistor202311,710,521Static random-access memory cell design202311,688,635Oxygen-free replacement liner for improved transistor performance202311,665,877Stacked FET SRAM design202311,658,116Interconnects on multiple sides of a semiconductor structure202311,652,156Nanosheet transistor with asymmetric gate stack202311,456,219Gate-all-around FETs having uniform threshold voltage202211,289,573Contact resistance reduction in nanosheet device structure202211,282,838Stacked gate structures202211,282,186Anomaly detection using image-based physical characterization202211,251,288Nanosheet transistor with asymmetric gate stack202211,201,153Stacked field effect transistor with wrap-around contacts202111,189,729Forming a sacrificial liner for dual channel devices202111,164,782Self-aligned gate contact compatible cross couple contact formation2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (39)· patent assignee history
2021Patents assigned to TESSERA INC (1)· patent assignee history
2021–2026Based in US· patent location history
2024–2026Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 39 | 2021–2026 |
| ADEIA SEMICONDUCTOR SOLUTIONS LLC | 2 | 2024–2026 |
| TESSERA INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 42 | 2021–2026 |