Inventor
Homare Sato
Inventor
Tokyo, JP
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores25%
H01LSemiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G06FElectric digital data processing9%
H10BElectronic memory devices7%
H10NElectric solid-state devices not otherwise provided for5%
H03KPulse technique4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
B08BCleaning in general2%
B60HArrangements of heating, cooling, ventilating or other air-treating devices specially adapted for passenger or goods spaces of vehicles2%
PatentTitleYear
11,073,215Gas supply system202110,985,035Substrate liquid processing apparatus, substrate liquid processing method and computer readable recording medium having substrate liquid processing program recorded therein202110,921,034Refrigeration cycle device202110,890,166Non-pulsation pump having stroke adjustment mechanism202110,636,461Apparatuses and methods for providing multiphase clock signals202010,553,263Memory device with write data bus control202010,489,312Stack access control for memory device201910,468,386TSV redundancy and TSV test select scheme201910,262,704Apparatuses and methods for providing multiphase clock signals201910,185,652Stack access control for memory device201910,163,469System and method for write data bus control in a stacked memory device20189,378,775'Semiconductor device including plural chips stacked to each other'20169,047,979'Semiconductor device including plural chips stacked to each other'20159,035,444'Semiconductor device having penetration electrodes penetrating through semiconductor chip'20158,885,430'Semiconductor memory device and data processing system'20148,797,822'Semiconductor device including plural chips stacked to each other'20148,681,525'Semiconductor device including plural chips stacked to each other'20148,331,122'Semiconductor device and information processing system including the same'20127,868,312'Semiconductor memory device and manufacturing method thereof'20117,842,976'Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer'20107,528,402'Electrically rewritable non-volatile memory element'20097,492,033'Semiconductor memory device'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2014Patents assigned to ELPIDA MEMORY INC (6)· patent assignee history
2009–2016Based in Tokyo, JP· patent location history
2012–2016Patents assigned to SATO HOMARE (6)· patent assignee history
2012–2016Patents assigned to HAYASHI JUNICHI (3)· patent assignee history
2014–2016Patents assigned to PS4 LUXCO SARL (5)· patent assignee history
2018–2020Patents assigned to MICRON TECHNOLOGY INC (7)· patent assignee history
2018–2020Based in Sagamihara, JP· patent location history
2021Based in Osaka, JP· patent location history
2021Based in Kumamoto, JP· patent location history
2021Based in Kariya, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 7 | 2018–2020 |
| ELPIDA MEMORY INC | 6 | 2009–2014 |
| SATO HOMAREself | 6 | 2012–2016 |
| PS4 LUXCO SARL | 5 | 2014–2016 |
| HAYASHI JUNICHI | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 11 | 2009–2016 |
| Sagamihara, JP | 6 | 2018–2020 |
| Osaka, JP | 1 | 2021 |
| Kumamoto, JP | 1 | 2021 |
| Kariya, JP | 1 | 2021 |