Inventor
Hisakatsu Yamaguchi
Inventor
Kawasaki, JP
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication32%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses14%
H03KPulse technique13%
H04BTransmission11%
G11CStatic stores7%
G06FElectric digital data processing5%
H03MCoding5%
G01RMeasuring electric variables4%
H03HImpedance networks, e.g. resonant circuits4%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner2%
PatentTitleYear
10,778,382Parameter setting transmission and reception system and parameter setting method202010,718,811Jitter measurement circuit and jitter measurement system202010,623,172Control signal transmission and reception system and control signal transmission and reception method20209,608,640'Receiving circuit and method for controlling frequency'20179,154,291'Differential signal skew adjustment method and transmission circuit'20159,088,405'Clock phase interpolator, data transmission and reception circuit, and method of clock phase interpolation'20158,638,843'Receiving device and receiving method'20148,588,340'Receiving device'20138,462,905'Receiver circuit'20138,325,864'Receiver circuit'20128,270,462'Adaptive equalizer circuit'20128,204,153'Clock recovery circuit and data receiving circuit'20128,065,553'Phase interpolator for a timing signal generating circuit'20117,982,638'Data transmission circuit and data communication system'20117,973,691'Data recovery circuit, data recovery method and data receiving apparatus'20117,936,296'AD converter, data receiver and data reception method'20117,880,543'Data transmitting circuit and transmitting method'20117,863,948'Clock frequency dividing circuit'20117,863,987'Clock signal generating and distributing apparatus'20117,786,785'Peaking control circuit'20107,653,169'Timing adjustment for data transmitting/receiving circuit'20107,542,532'Data transmission device and input/output interface circuit'20097,542,506'Data receiver and equalizer adapter'20097,535,956'Adaptive equalizer circuit'20097,515,656'Clock recovery circuit and data receiving circuit'20097,496,781'Timing signal generating circuit with a master circuit and slave circuits'20097,397,293'Clock distribution circuit'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to FUJITSU LTD (27)· patent assignee history
2008–2020Based in Kawasaki, JP· patent location history
2011–2014Patents assigned to YAMAGUCHI HISAKATSU (7)· patent assignee history
2011–2012Patents assigned to GOTOH KOHTAROH (2)· patent assignee history
2013–2014Patents assigned to FUJITSU SEMICONDUCTOR LTD (2)· patent assignee history
2013–2014Patents assigned to KAWAHARA SATOSHI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 27 | 2008–2020 |
| YAMAGUCHI HISAKATSUself | 7 | 2011–2014 |
| FUJITSU SEMICONDUCTOR LTD | 2 | 2013–2014 |
| GOTOH KOHTAROH | 2 | 2011–2012 |
| KAWAHARA SATOSHI | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 27 | 2008–2020 |