Inventor
David P. Chengson
Inventor
Aptos, CA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication25%
H05KPrinted circuits16%
G06FElectric digital data processing14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H03KPulse technique9%
G01RMeasuring electric variables5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%
H04JMultiplex communication5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
G05FSystems for regulating electric or magnetic variables2%
PatentTitleYear
10,455,691Grid array pattern for crosstalk reduction201910,455,690Grid array pattern for crosstalk reduction201910,383,213Placement of vias in printed circuit board circuits201910,365,314Electrical signature fault detection201910,231,325Placement of vias in printed circuit board circuits201910,069,596Systems and methods for error detection and correction20189,237,003'Digital bit insertion for clock recovery'20168,675,483'Systems and methods for reducing reflections and frequency dependent dispersions in redundant links'20148,508,248'Testing vias formed in printed circuit boards'20138,452,908'Low latency serial memory interface'20138,411,695'Multi-interface compatible bus over a common physical connection'20138,164,392'Error-free startup of low phase noise oscillators'20128,000,351'Source synchronous link with clock recovery and bit skew alignment'20117,924,862'Systems and methods for reducing reflections and frequency dependent dispersions in redundant links'20117,724,761'Systems and methods for reducing reflections and frequency dependent dispersions in redundant links'20107,515,614'Source synchronous link with clock recovery and bit skew alignment'20097,061,939'Source synchronous link with clock recovery and bit skew alignment'20066,646,982'Redundant source synchronous busses'20036,538,518'Multi-loop phase lock loop for controlling jitter in a high frequency redundant system'20035,999,437'Processor-inclusive memory module'19995,867,419'Processor-inclusive memory module'19995,811,997'Multi-configurable push-pull/open-drain driver circuit'19985,793,259'Apparatus for generating differential noise between power and ground planes'19985,790,612'System and method to reduce jitter in digital delay-locked loops'19985,710,733'Processor-inclusive memory module'19985,041,747'Delay regulation circuit'19915,036,528'Self-calibrating clock synchronization system'19914,728,818'Emitter function logic with concurrent, complementary outputs'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–1991Patents assigned to TANDEM COMPUTERS INC (3)· patent assignee history
1988–1991Based in Mountain View, CA, US· patent location history
1998–1999Patents assigned to SILICON GRAPHICS INC (6)· patent assignee history
1998–2019Based in Aptos, CA, US· patent location history
2003–2019Patents assigned to JUNIPER NETWORKS INC (18)· patent assignee history
2003–2014Based in Scotts Valley, CA, US· patent location history
2012–2016Patents assigned to CHENGSON DAVID P (5)· patent assignee history
2013–2014Patents assigned to BANDYOPADHYAY JAYA (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| JUNIPER NETWORKS INC | 18 | 2003–2019 |
| SILICON GRAPHICS INC | 6 | 1998–1999 |
| CHENGSON DAVID Pself | 5 | 2012–2016 |
| TANDEM COMPUTERS INC | 3 | 1988–1991 |
| BANDYOPADHYAY JAYA | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Aptos, California, US | 16 | 1998–2019 |
| Scotts Valley, California, US | 9 | 2003–2014 |
| Mountain View, California, US | 3 | 1988–1991 |