Inventor

Griselda Bonilla

Inventor

Fishkill, NY, US

Overview

2008–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 93 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1042%

H01LSemiconductor devices27%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10DInorganic electric semiconductor devices6%

G01RMeasuring electric variables4%

H01HElectric switches2%

Y10TTechnical subjects covered by former us classification2%

B82YSpecific uses or applications of nanostructures1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

G11CStatic stores0%

PatentTitleYear

10,964,647Dielectric crack stop for advanced interconnects2021 10,957,657Advanced crack stop structure2021 10,847,475Advanced crack stop structure2020 10,840,195Advanced crack stop structure2020 10,840,194Advanced crack stop structure2020 10,734,475Stacked MIM capacitors with self-aligned contact to reduce via enclosure2020 10,490,513Advanced crack stop structure2019 10,475,753Advanced crack stop structure2019 10,396,042Dielectric crack stop for advanced interconnects2019 10,366,940Air gap and air spacer pinch off2019 10,256,186Interconnect structure having subtractive etch feature and damascene feature2019 10,256,171Air gap and air spacer pinch off2019 10,242,933Air gap and air spacer pinch off2019 10,229,875Stacked via structure for metal fuse applications2019 10,224,236Forming air gap2019 10,177,076Air gap and air spacer pinch off2019 10,177,031Subtractive etch interconnects2019 10,103,068Detecting a void between a via and a wiring line2018 9,893,011'Back-end electrically programmable fuse'2018 9,852,980Interconnect structure having substractive etch feature and damascene feature2017 9,793,193'Air gap and air spacer pinch off'2017 9,786,760'Air gap and air spacer pinch off'2017 9,759,766'Electromigration test structure for Cu barrier integrity and blech effect evaluations'2017 9,685,404'Back-end electrically programmable fuse'2017 9,673,089'Interconnect structure with enhanced reliability'2017 9,601,426'Interconnect structure having subtractive etch feature and damascene feature'2017 9,536,830'High performance refractory metal / copper interconnects to eliminate electromigration'2017 9,536,842'Structure with air gap crack stop'2017 9,502,350'Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer'2016 9,472,477'Electromigration test structure for Cu barrier integrity and blech effect evaluations'2016 9,472,450'Graphene cap for copper interconnect structures'2016 9,455,186'Selective local metal cap layer formation for improved electromigration behavior'2016 9,431,346'Graphene-metal E-fuse'2016 9,431,292'Alternate dual damascene method for forming interconnects'2016 9,425,144'Metal fuse structure for improved programming capability'2016 9,406,560'Selective local metal cap layer formation for improved electromigration behavior'2016 9,385,038'Selective local metal cap layer formation for improved electromigration behavior'2016 9,360,525'Stacked via structure for metal fuse applications'2016 9,324,655'Modified via bottom for beol via efuse'2016 9,293,412'Graphene and metal interconnects with reduced contact resistance'2016 9,287,185'Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations'2016 9,257,391'Hybrid graphene-metal interconnect structures'2016 9,202,743'Graphene and metal interconnects'2015 9,171,801'E-fuse with hybrid metallization'2015 9,142,506'E-fuse structures and methods of manufacture'2015 9,105,638'Via-fuse with low dielectric constant'2015 9,105,642'Interlevel dielectric stack for interconnect structures'2015 9,099,468'Electronic fuse vias in interconnect structures'2015 9,093,452'Electronic fuse with resistive heater'2015 9,093,164'Redundant via structure for metal fuse applications'2015 9,076,847'Selective local metal cap layer formation for improved electromigration behavior'2015 9,059,169'E-fuse structures and methods of manufacture'2015 9,059,170'Electronic fuse having a damaged region'2015 9,034,664'Method to resolve hollow metal defects in interconnects'2015 9,018,089'Multiple step anneal method and semiconductor formed by multiple step anneal'2015 9,018,767'Interlevel dielectric stack for interconnect structures'2015 8,962,467'Metal fuse structure for improved programming capability'2015 8,921,167'Modified via bottom for BEOL via efuse'2014 8,916,461'Electronic fuse vias in interconnect structures'2014 8,912,658'Interconnect structure with enhanced reliability'2014 8,895,433'Method of forming a graphene cap for copper interconnect structures'2014 8,836,124'Fuse and integrated conductor'2014 8,809,183'Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer'2014 8,796,133'Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections'2014 8,779,600'Interlevel dielectric stack for interconnect structures'2014 8,742,766'Stacked via structure for metal fuse applications'2014 8,736,020'Electronic anti-fuse'2014 8,633,707'Stacked via structure for metal fuse applications'2014 8,623,761'Method of forming a graphene cap for copper interconnect structures'2014 8,481,423'Methods to mitigate plasma damage in organosilicate dielectrics'2013 8,470,706'Methods to mitigate plasma damage in organosilicate dielectrics'2013 8,421,239'Crenulated wiring structure and method for integrated circuit interconnects'2013 8,298,948'Capping of copper interconnect lines in integrated circuit devices'2012 8,232,646'Interconnect structure for integrated circuits having enhanced electromigration resistance'2012 8,026,166'Interconnect structures comprising capping layers with low dielectric constants and methods of making the same'2011 8,003,520'Air gap structure having protective metal silicide pads on a metal feature'2011 7,884,477'Air gap structure having protective metal silicide pads on a metal feature'2011 7,847,402'BEOL interconnect structures with improved resistance to stress'2010 7,795,740'Adhesion enhancement for metal/dielectric interface'2010 7,776,737'Reliability of wide interconnects'2010 7,749,892'Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices'2010 7,737,029'Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby'2010 7,737,052'Advanced multilayer dielectric cap with improved mechanical and electrical properties'2010 7,737,528'Structure and method of forming electrically blown metal fuses for integrated circuits'2010 7,671,470'Enhanced mechanical strength via contacts'2010 7,670,943'Enhanced mechanical strength via contacts'2010 7,666,753'Metal capping process for BEOL interconnect with air gaps'2010 7,629,264'Structure and method for hybrid tungsten copper metal contact'2009 7,573,130'Crack trapping and arrest in thin film structures'2009 7,514,361'Selective thin metal cap process'2009 7,491,578'Method of forming crack trapping and arrest in thin film structures'2009 7,446,058'Adhesion enhancement for metal/dielectric interface'2008 7,439,624'Enhanced mechanical strength via contacts'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2021Patents assigned to IBM (84)· patent assignee history

2008–2019Based in Fishkill, NY, US· patent location history

2012–2017Patents assigned to BONILLA GRISELDA (20)· patent assignee history

2012–2017Patents assigned to SIMON ANDREW H (11)· patent assignee history

2012–2017Patents assigned to CHANDA KAUSHIK (9)· patent assignee history

2012–2021Based in Hopewell Junction, NY, US· patent location history

2016–2019Patents assigned to GLOBALFOUNDRIES INC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	84	2008–2021
BONILLA GRISELDAself	20	2012–2017
SIMON ANDREW H	11	2012–2017
GLOBALFOUNDRIES INC	10	2016–2019
CHANDA KAUSHIK	9	2012–2017

Locations

Location	Patents	Span
Fishkill, New York, US	66	2008–2019
Hopewell Junction, New York, US	27	2012–2021