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Inventor

Myron Buer

Inventor
Gilbert, AZ, US

Overview

43→
Patents
1998–2017
Patent span
Physics
Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores61%
H10BElectronic memory devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing5%
H03KPulse technique2%
PatentTitleYear
9,767,891'Passive SRAM write assist'20179,753,667'High bandwidth memory and glitch-less differential XOR'20179,659,624'Method for sense reference generation for MTJ based memories'20179,286,997'Read only memory array architecture and methods of operation'20168,976,616'Multi-time programmable memory'20158,830,721'Encoded read-only memory (ROM) bitcell, array, and architecture'20148,705,268'Quantifying the read and write margins of memory bit cells'20148,659,955'Memory array having word lines with folded architecture'20148,462,575'Multi-time programmable memory'20138,406,031'Read-only memory (ROM) bitcell, array, and architecture'20138,300,493'Encoded read-only memory (ROM) decoder'20128,094,499'Method using a one-time programmable memory cell'20128,089,821'Memory device using antifuses'20128,040,748'Quad SRAM based one time programmable memory'20117,986,570'Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme'20117,940,593'Method and apparatus for verification of a gate oxide fuse element'20117,897,967'Anti-fuse device'20117,796,418'Programmable memory cell'20107,715,265'Differential latch-based one time programmable memory'20107,649,798'Memory device using antifuses'20107,639,549'Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme'20097,609,578'Quad SRAM based one time programmable memory'20097,376,022'Method using a one-time programmable memory cell'20087,251,175'Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme'20077,136,303'System and method using a one-time programmable memory cell'20067,009,883'Automatic programming time selection for one time programmable memory'20066,902,958'Method for making MOSFET anti-fuse structure'20056,903,993'Memory cell with fuse element'20056,901,004'High voltage switch circuitry'20056,898,103'Memory cell with fuse element'20056,856,531'Hacker-proof one time programmable memory'20056,822,918'Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme'20046,744,660'High voltage switch circuitry'20046,707,696'Hacker-proof one time programmable memory'20046,704,236'Method and apparatus for verification of a gate oxide fuse element'20046,700,176'MOSFET anti-fuse structure and method for making same'20046,693,819'High voltage switch circuitry'20046,639,866'Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme'20036,525,955'Memory cell with fuse element'20036,442,061'Single channel four transistor SRAM'20026,018,480'Method and system which permits logic signal routing over on-chip memories'20005,808,900'Memory having direct strap connection to power supply'19985,748,070'High speed method and apparatus for detecting assertion of multiple signals'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2002Patents assigned to LSI LOGIC CORP (4)· patent assignee history
1998Based in Eden Prairie, MN, US· patent location history
2000–2002Based in Shakopee, MN, US· patent location history
2003–2017Patents assigned to BROADCOM CORP (38)· patent assignee history
2003–2012Based in Gilbert, AZ, US· patent location history
2012–2014Patents assigned to BUER MYRON (7)· patent assignee history
2012–2013Patents assigned to SUN DECHANG (2)· patent assignee history
2012–2017Based in Savage, MN, US· patent location history
2017Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (3)· patent assignee history
2017Based in Prior Lake, MN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
BROADCOM CORP382003–2017
BUER MYRONself72012–2014
LSI LOGIC CORP41998–2002
AVAGO TECHNOLOGIES GENERAL IP32017
SUN DECHANG22012–2013
Locations
LocationPatentsSpan
Gilbert, AZ, US282003–2012
Savage, Minnesota, US102012–2017
Shakopee, Minnesota, US22000–2002
Eden Prairie, Minnesota, US21998
Prior Lake, Minnesota, US12017