Inventor
RAHUL MANEPALLI
Inventor
US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H05KPrinted circuits5%
C08JWorking-up2%
C23CCoating metallic material2%
C25DProcesses for the electrolytic or electrophoretic production of coatings2%
F16BDevices for fastening or securing constructional elements or machine parts together, e.g. nails, bolts, circlips, clamps, clips or wedges2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
12,568,831Patternable die attach materials and processes for patterning202612,416,093Electroless plating process202512,341,117Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates202512,308,329Chiplet first architecture for die tiling applications202512,243,825Hybrid conductive vias for electronic substrates202512,159,825Dielectric-to-metal adhesion promotion material202412,125,793Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202412,087,695Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202411,990,427Chiplet first architecture for die tiling applications202411,978,685Glass core patch with in situ fabricated fan-out layer to enable die tiling applications202411,973,041Chiplet first architecture for die tiling applications202411,923,312Patternable die attach materials and processes for patterning202411,769,735Chiplet first architecture for die tiling applications202311,756,890Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202311,694,898Hybrid fine line spacing architecture for bump pitch scaling202311,658,055Customizable release layers to enable low warpage architectures for advanced packaging applications202311,646,274Multi-package assemblies having foam structures for warpage control202311,501,967Selective metal deposition by patterning direct electroless metal plating202211,445,616Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures202211,355,438Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications202211,177,234Package architecture with improved via drill process and method for forming such package2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (21)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 21 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 21 | 2021–2026 |