Inventor
Francis X. McKeen
Inventor
Portland, OR, US
Overview
Patents· 112 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
H04LTransmission of digital information, e.g. telegraphic communication13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy2%
G11CStatic stores1%
PatentTitleYear
11,055,236Processors, methods, systems, and instructions to support live migration of protected containers202111,030,120Host-convertible secure enclaves in memory that leverage multi-key total memory encryption with integrity202110,970,390Mechanism to prevent software side channels202110,922,241Supporting secure memory intent202110,922,088Processor instruction support to defeat side-channel attacks202110,885,202Method and apparatus to provide secure application execution202110,880,097Flexible provisioning of attestation keys in secure enclaves202010,708,067Platform attestation and registration for servers202010,671,542Application execution enclave memory method and apparatus202010,671,740Supporting configurable security levels for memory address ranges202010,628,315Secure memory repartitioning technologies202010,621,336Technologies for software attack detection using encoded access intent202010,592,421Instructions and logic to provide advanced paging capabilities for secure enclave page caches202010,592,436Memory initialization in a protected region202010,558,588Processors, methods, systems, and instructions to support live migration of protected containers202010,552,344Unblock instruction to reverse page block during paging202010,540,291Tracking and managing translation lookaside buffers202010,534,724Instructions and logic to suspend/resume migration of enclaves in a secure enclave page cache202010,409,597Memory management in secure enclaves201910,338,957Provisioning keys for virtual machine secure enclaves201910,324,862Supporting oversubscription of guest enclave memory pages201910,325,118Cryptographic cache lines for a trusted execution environment201910,289,554Supporting fault information delivery201910,282,306Supporting secure memory intent201910,230,528Tree-less integrity and replay memory protection for trusted execution environment201910,216,648Maintaining a secure processing environment across power cycles201910,152,350Secure domain manager201810,135,622Flexible provisioning of attestation keys in secure enclaves201810,120,805Managing memory for secure enclaves201810,102,380Method and apparatus to provide secure application execution201810,019,601Method and apparatus for securely saving and restoring the state of a computing platform20189,990,197Memory management in secure enclaves20189,990,314Instructions and logic to interrupt and resume paging in a secure enclave page cache20189,977,743Managing enclave memory pages20189,971,705Virtual memory address range register20189,959,418Supporting configurable security levels for memory address ranges20189,942,035Platform migration of secure enclaves20189,904,632'Technique for supporting multiple secure enclaves'20189,904,805'Cryptographic cache lines for a trusted execution environment'20189,875,189Supporting secure memory intent20189,798,666'Supporting fault information delivery'20179,767,044'Secure memory repartitioning'20179,766,889'Memory management in secure enclaves'20179,747,102'Memory management in secure enclaves'20179,716,710'Technologies for virtualized access to security services provided by a converged manageability and security engine'20179,710,401'Processors, methods, systems, and instructions to support live migration of protected containers'20179,703,733'Instructions and logic to interrupt and resume paging in a secure enclave page cache'20179,698,989'Feature licensing in a secure processing environment'20179,690,704'Paging in secure enclaves'20179,684,608'Maintaining a secure processing environment across power cycles'20179,665,724'Logging in secure enclaves'20179,519,803'Secure environment for graphics processing units'20169,448,950'Using authenticated manifests to enable external certification of multi-processor platforms'20169,430,384'Instructions and logic to provide advanced paging capabilities for secure enclave page caches'20169,407,636'Method and apparatus for securely saving and restoring the state of a computing platform'20169,355,262'Modifying memory permissions in a secure processing environment'20169,323,686'Paging in secure enclaves'20169,286,235'Virtual memory address range register'20169,276,750'Secure processing environment measurement and attestation'20169,189,411'Logging in secure enclaves'20159,183,161'Apparatus and method for page walk extension for enhanced security checks'20159,087,200'Method and apparatus to provide secure application execution'20159,076,019'Method and apparatus for memory encryption with integrity check and protection against replay attacks'20158,972,746'Technique for supporting multiple secure enclaves'20158,671,275'Mechanism to handle events in a machine with isolated execution'20148,522,044'Mechanism to handle events in a machine with isolated execution'20138,458,464'Mechanism to handle events in a machine with isolated execution'20138,028,341'Providing extended memory protection'20117,793,111'Mechanism to handle events in a machine with isolated execution'20107,673,345'Providing extended memory protection'20107,565,492'Method and apparatus for preventing software side channel attacks'20097,389,427'Mechanism to secure computer output from software attack using isolated execution'20087,380,278'Protecting software environment in isolated execution'20087,275,263'Method and system and authenticating a user of a computer system that has a trusted platform module (TPM)'20077,254,707'Platform and method for remote attestation of a platform'20077,194,634'Attestation key memory device and bus'20077,111,176'Generating isolated bus cycles for isolated execution'20067,096,497'File checking using remote signing authority via a network'20067,089,418'Managing accesses in a processor for isolated execution'20067,085,935'Managing a secure environment using a chipset in isolated execution mode'20067,082,615'Protecting software environment in isolated execution'20067,073,071'Platform and method for generating and utilizing a protected audit log'20067,013,484'Managing a secure environment using a chipset in isolated execution mode'20067,013,481'Attestation key memory device and bus'20066,996,710'Platform and method for issuing and certifying a hardware-protected attestation key'20066,990,579'Platform and method for remote attestation of a platform'20066,981,129'Breaking replay dependency loops in a processor using a rescheduled replay queue'20056,957,332'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'20056,941,458'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'20056,934,817'Controlling access to multiple memory zones in an isolated execution environment'20056,877,086'Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter'20056,795,905'Controlling accesses to isolated memory using a memory controller for isolated execution'20046,769,058'Resetting a processor in an isolated execution environment'20046,760,441'Generating a key hieararchy for use in an isolated execution environment'20046,754,815'Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set'20046,704,861'Mechanism for executing computer instructions in parallel'20046,678,825'Controlling access to multiple isolated memories in an isolated execution environment'20046,633,963'Controlling access to multiple memory zones in an isolated execution environment'20036,507,904'Executing isolated mode instructions in a secure system running in privilege rings'20036,154,828'Method and apparatus for employing a cycle bit parallel executing instructions'20005,428,807'Method and apparatus for propagating exception conditions of a computer system'19955,420,990'Mechanism for enforcing the correct order of instruction execution'19955,421,022'Apparatus and method for speculatively executing instructions in a computer system'19955,285,323'Integrated circuit chip having primary and secondary random access memories for a hierarchical cache'19945,168,573'Memory device for storing vector registers'19925,113,521'Method and apparatus for handling faults of vector instructions causing memory management exceptions'19925,109,495'Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor'19925,067,069'Control of multiple functional units with parallel operation in a microcoded execution unit'19914,985,825'System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer'19914,980,817'Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports'19904,947,358'Normalizer for determining the positions of bits that are set in a mask'19904,888,679'Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–1995Patents assigned to DIGITAL EQUIPMENT CORP (11)· patent assignee history
1989–1992Based in Westboro, MA, US· patent location history
1992–2004Based in Westborough, MA, US· patent location history
2003–2021Patents assigned to INTEL CORP (98)· patent assignee history
2003–2021Based in Portland, OR, US· patent location history
2013–2016Patents assigned to MCKEEN FRANCIS X (8)· patent assignee history
2015–2016Patents assigned to ROZAS CARLOS V (5)· patent assignee history
2015–2016Patents assigned to ANATI ITTAI (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 98 | 2003–2021 |
| DIGITAL EQUIPMENT CORP | 11 | 1989–1995 |
| MCKEEN FRANCIS Xself | 8 | 2013–2016 |
| ROZAS CARLOS V | 5 | 2015–2016 |
| ANATI ITTAI | 4 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 98 | 2003–2021 |
| Westborough, Massachusetts, US | 7 | 1992–2004 |
| Westboro, Massachusetts, US | 7 | 1989–1992 |