Inventor
Shailesh Shah
Inventor
San Jose, CA, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing25%
H03KPulse technique25%
G11CStatic stores20%
A61KPreparations for medical, dental or toiletry purposes5%
A61MDevices for introducing media into, or onto, the body5%
C07CAcyclic or carbocyclic compounds5%
H03MCoding5%
H04LTransmission of digital information, e.g. telegraphic communication5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
PatentTitleYear
11,020,361Nasal formulations of metoclopramide20219,075,741'Dynamic error handling using parity and redundant rows'20157,221,200'Programmable low voltage reset apparatus for multi-Vdd chips'20077,170,179'Chip select method through double bonding'20076,822,899'Method of protecting flash memory from data corruption during fast power down events'20046,523,055'Circuit and method for multiplying and accumulating the sum of two products in a single cycle'20036,222,393'Apparatus and method for generating a pulse signal'20015,987,603'Apparatus and method for reversing bits using a shifter'19995,933,032'Apparatus and method for generating a pulse signal'19995,903,174'Method and apparatus for reducing skew among input signals within an integrated circuit'19995,835,401'Dram with hidden refresh'19985,835,970'Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses'19985,652,732'Apparatus and method for matching a clock delay to a delay through a memory array'19975,559,465'Output preconditioning circuit with an output level latch and a clamp'19965,490,115'Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2007Patents assigned to CYPRESS SEMICONDUCTOR CORP (11)· patent assignee history
1996–2007Based in San Jose, CA, US· patent location history
1999–2003Patents assigned to LSI LOGIC CORP (2)· patent assignee history
1999–2003Based in Sunnyvale, CA, US· patent location history
2015Patents assigned to DAMARAJU SATISH K (1)· patent assignee history
2015Patents assigned to INTEL CORP (1)· patent assignee history
2015Based in Folsom, CA, US· patent location history
2021Patents assigned to EVOKE PHARMA INC (1)· patent assignee history
2021Based in Phoenix, AZ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 11 | 1996–2007 |
| LSI LOGIC CORP | 2 | 1999–2003 |
| DAMARAJU SATISH K | 1 | 2015 |
| EVOKE PHARMA INC | 1 | 2021 |
| INTEL CORP | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 11 | 1996–2007 |
| Sunnyvale, California, US | 2 | 1999–2003 |
| Phoenix, AZ, US | 1 | 2021 |
| Folsom, California, US | 1 | 2015 |