Inventor
Mark G. Johnson
Inventor
Los Altos, CA, US
Overview
Patents· 69 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
H10BElectronic memory devices17%
G06FElectric digital data processing9%
H10DInorganic electric semiconductor devices9%
H03KPulse technique6%
H10NElectric solid-state devices not otherwise provided for5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H01LSemiconductor devices4%
PatentTitleYear
11,047,726Fluid level sensing device and method of determining a fluid level comprising an optical waveguide with successive ones of curved portions being curved in alternating directions20219,214,243'Three-dimensional nonvolatile memory and method of fabrication'20159,171,857'Dense arrays and charge storage devices'20158,981,457'Dense arrays and charge storage devices'20158,897,056'Pillar-shaped nonvolatile memory and method of fabrication'20148,853,765'Dense arrays and charge storage devices'20148,823,076'Dense arrays and charge storage devices'20148,575,719'Silicon nitride antifuse for use in diode-antifuse memory arrays'20138,503,215'Vertically stacked field programmable nonvolatile memory and method of fabrication'20138,458,426'Transceiver with latency alignment circuitry'20138,208,282'Vertically stacked field programmable nonvolatile memory and method of fabrication'20128,086,812'Transceiver with latency alignment circuitry'20117,978,492'Integrated circuit incorporating decoders disposed beneath memory arrays'20117,863,950'Apparatus for adaptive trip point detection'20117,863,951'Methods for adaptive trip point detection'20117,825,455'Three terminal nonvolatile memory device with vertical gated diode'20107,383,476'System architecture and method for three-dimensional memory'20087,308,065'Delay locked loop circuitry for clock delay adjustment'20077,283,403'Memory device and method for simultaneously programming and/or reading memory cells on different levels'20077,236,023'Apparatus and methods for adaptive trip point detection'20077,203,084'Three-dimensional memory device with ECC circuitry'20077,190,602'Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement'20077,177,183'Multiple twin cell non-volatile memory array and logic block structure and method therefor'20077,129,538'Dense arrays and charge storage devices'20067,124,270'Transceiver with latency alignment circuitry'20067,091,529'Three-dimensional memory array and method of fabrication'20067,065,622'Transceiver with latency alignment circuitry'20067,039,147'Delay locked loop circuitry for clock delay adjustment'20067,010,658'Transceiver with latency alignment circuitry'20066,996,017'Redundant memory structure using bad bit pointers'20066,954,394'Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions'20056,901,549'Method for altering a word stored in a write-once memory device'20056,888,750'Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication'20056,881,994'Monolithic three dimensional array of charge storage devices containing a planarized surface'20056,868,022'Redundant memory structure using bad bit pointers'20056,867,992'Modular memory device'20056,780,683'Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication'20046,780,711'Vertically stacked field programmable nonvolatile memory and method of fabrication'20046,689,644'Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication'20046,653,712'Three-dimensional memory array and method of fabrication'20036,643,752'Transceiver with latency alignment circuitry'20036,631,085'Three-dimensional memory array incorporating serial chain diode stack'20036,624,485'Three-dimensional, mask-programmed read only memory'20036,591,394'Three-dimensional memory array and method for storing data bits and ECC bits therein'20036,545,891'Modular memory device'20036,539,072'Delay locked loop circuitry for clock delay adjustment'20036,525,949'Charge pump circuit'20036,525,953'Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication'20036,515,888'Low cost three-dimensional memory array'20036,483,728'Charge pump circuit'20026,483,736'Vertically stacked field programmable nonvolatile memory and method of fabrication'20026,420,215'Three-dimensional memory array and method of fabrication'20026,385,074'Integrated circuit structure including three-dimensional memory array'20026,351,406'Vertically stacked field programmable nonvolatile memory and method of fabrication'20026,185,122'Vertically stacked field programmable nonvolatile memory and method of fabrication'20016,157,244'Power supply independent temperature sensor'20006,125,157'Delay-locked loop circuitry for clock delay adjustment'20006,107,847'Zero power reset circuit for low voltage CMOS circuits'20006,057,739'Phase-locked loop with variable parameters'20006,034,882'Vertically stacked field programmable nonvolatile memory and method of fabrication'20005,961,215'Temperature sensor integral with microprocessor and methods of using same'19995,614,855'Delay-locked loop'19975,488,321'Static high speed comparator'19965,451,898'Bias circuit and differential amplifier having stabilized output swing'19955,327,381'Redundancy selection apparatus and method for an array'19945,101,117'Variable delay line phase-locked loop circuit synchronization system'19924,829,481'Defective element disabling circuit having a laser-blown fuse'19894,618,786'Precharge circuit for enhancement mode memory circuits'19864,523,110'MOSFET sense amplifier circuit'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–1989Based in Dallas, TX, US· patent location history
1986–1994Based in Sunnyvale, CA, US· patent location history
1995–2013Patents assigned to RAMBUS INC (14)· patent assignee history
1995–2015Based in Los Altos, CA, US· patent location history
1999–2000Patents assigned to ADVANCED MICRO DEVICES INC (3)· patent assignee history
2000–2006Patents assigned to MATRIX SEMICONDUCTOR INC (25)· patent assignee history
2006–2015Patents assigned to SANDISK 3D LLC (21)· patent assignee history
2012–2015Patents assigned to JOHNSON MARK G (4)· patent assignee history
2021Based in London, GB· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MATRIX SEMICONDUCTOR INC | 25 | 2000–2006 |
| SANDISK 3D LLC | 21 | 2006–2015 |
| RAMBUS INC | 14 | 1995–2013 |
| JOHNSON MARK Gself | 4 | 2012–2015 |
| ADVANCED MICRO DEVICES INC | 3 | 1999–2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 63 | 1995–2015 |
| Sunnyvale, California, US | 3 | 1986–1994 |
| Dallas, Texas, US | 2 | 1985–1989 |
| London, GB | 1 | 2021 |