LexDanaLexDanabeta
Inventor

Jenn Ming Huang

Inventor
Hsinchu, TW

Overview

70→
Patents
1996–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices28%
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H02JElectric power networks1%
F28CHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media come into direct contact without chemical interaction1%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact1%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application1%
PatentTitleYear
10,931,147Hybrid power converter202110,892,645Current sense apparatus and method20217,119,017'Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios'20067,037,776'Single polysilicon process for DRAM'20067,030,440'Single poly-si process for DRAM by deep N-well (NW) plate'20066,825,078'Single poly-Si process for DRAM by deep N well (NW) plate'20046,818,495'Method for forming high purity silicon oxide field oxide isolation region'20046,617,631'Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device'20036,600,228'Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule'20036,579,784'Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers'20036,436,763'Process for making embedded DRAM circuits having capacitor under bit-line (CUB)'20026,406,987'Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions'20026,353,269'Method for making cost-effective embedded DRAM structures compatible with logic circuit processing'20026,351,016'Technology for high performance buried contact and tungsten polycide gate integration'20026,294,456'Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule'20016,274,471'Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique'20016,265,120'Geometry design of active region to improve junction breakdown and field isolation in STI process'20016,255,160'Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells'20016,251,726'Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar'20016,235,593'Self aligned contact using spacers on the ILD layer sidewalls'20016,228,699'Cross leakage of capacitors in DRAM or embedded DRAM'20016,221,713'Approach for self-aligned contact and pedestal'20016,198,173'SRAM with improved Beta ratio'20016,187,624'Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device'20016,159,786'Well-controlled CMP process for DRAM technology'20006,157,064'Method and a deep sub-micron field effect transistor structure for suppressing short channel effects'20006,137,179'Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines'20006,127,260'Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices'20006,117,725'Method for making cost-effective embedded DRAM structures compatible with logic circuit processing'20006,117,723'Salicide integration process for embedded DRAM devices'20006,103,622'Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device'20006,103,621'Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device'20006,100,116'Method to form a protected metal fuse'20006,100,118'Fabrication of metal fuse design for redundancy technology having a guard ring'20006,096,595'Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices'20006,093,640'Overlay measurement improvement between damascene metal interconnections'20006,074,908'Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits'20006,042,999'Robust dual damascene process'20006,037,222'Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology'20006,037,199'SOI device for DRAM cells beyond gigabit generation and method for making the same'20006,033,999'Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal'20006,033,963'Method of forming a metal gate for CMOS devices using a replacement gate process'20006,025,279'Method of reducing nitride and oxide peeling after planarization using an anneal'20006,015,730'Integration of SAC and salicide processes by combining hard mask and poly definition'20006,015,735'Method for forming a multi-anchor DRAM capacitor and capacitor formed'20006,004,843'Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip'19996,001,721'Silicide and salicide on the same chip'19995,998,269'Technology for high performance buried contact and tungsten polycide gate integration'19995,998,252'Method of salicide and sac (self-aligned contact) integration'19995,989,966'Method and a deep sub-micron field effect transistor structure for suppressing short channel effects'19995,989,954'Method for forming a cylinder capacitor in the dram process'19995,963,839'Reduction of polysilicon contact resistance by nitrogen implantation'19995,924,011'Silicide process for mixed mode product'19995,918,120'Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines'19995,918,119'Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure'19995,899,722'Method of forming dual spacer for self aligned contact integration'19995,872,030'Method of improving beta ratio in SRAM and device manufactured thereby'19995,863,820'Integration of sac and salicide processes on a chip having embedded memory'19995,854,119'Robust method of forming a cylinder capacitor for DRAM circuits'19985,834,811'Salicide process for FETs'19985,828,111'Increase resistance of a polysilicon load resistor, in an SRAM cell'19985,821,141'Method for forming a cylindrical capacitor in DRAM having pin plug profile'19985,726,932'Trench free SRAM cell structure'19985,721,166'Method to increase the resistance of a polysilicon load resistor, in an SRAM cell'19985,646,057'Method for a MOS device manufacturing'19975,607,881'Method of reducing buried contact resistance in SRAM'19975,596,215'Method to improve buried contact resistance'19975,554,549'Salicide process for FETs'19965,525,552'Method for fabricating a MOSFET device with a buried contact'19965,494,843'Method for forming MOSFET devices'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2006Patents assigned to TAIWAN SEMICONDUCTOR MFG (67)· patent assignee history
1996–2006Based in Hsinchu, TW· patent location history
1999Based in Hsin Chu, TW· patent location history
1999Based in Chinchu, TW· patent location history
1999Based in Taiwan, TW· patent location history
2021Patents assigned to NUVOLTA TECH HEFEI CO LTD (2)· patent assignee history
2021Patents assigned to X2 POWER TECH LIMITED (2)· patent assignee history
2021Based in Nashua, NH, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG671996–2006
NUVOLTA TECH HEFEI CO LTD22021
X2 POWER TECH LIMITED22021
Locations
LocationPatentsSpan
Hsinchu, TW641996–2006
Nashua, NH, US22021
Hsin Chu, TW11999
Chinchu, TW11999
Taiwan, TW11999