LexDanaLexDanabeta
Inventor

Eric A. Joseph

Inventor
White Plains, NY, US

Overview

93→
Patents
2003–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 93 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices20%
H10NElectric solid-state devices not otherwise provided for17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10BElectronic memory devices7%
H10DInorganic electric semiconductor devices7%
G11CStatic stores4%
H01JElectric discharge tubes or discharge lamps3%
B82YSpecific uses or applications of nanostructures2%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
PatentTitleYear
10,727,114Interconnect structure including airgaps and substractively etched metal lines202010,727,121Thin film interconnects with large grains202010,643,859Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication202010,607,899Nano deposition and ablation for the repair and fabrication of integrated circuits202010,600,656Directed self-assembly for copper patterning202010,529,633Method of integrated circuit (IC) chip fabrication202010,388,857Spin torque MRAM fabrication using negative tone lithography and ion beam etching201910,276,439Rapid oxide etch for manufacturing through dielectric via structures201910,236,252Hybrid subtractive etch/metal fill process for fabricating interconnects201910,170,698Spin torque MRAM fabrication using negative tone lithography and ion beam etching201910,170,361Thin film interconnects with large grains201910,167,443Wet clean process for removing C201910,128,185Hybrid subtractive etch/metal fill process for fabricating interconnects201810,121,676Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch20189,934,984Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication20189,911,648'Interconnects based on subtractive etching of silver'20189,799,519'Selective sputtering with light mass ions to sharpen sidewall of subtractively patterned conductive metal layer'20179,799,552'Low resistance metal contacts to interconnects'20179,786,597'Self-aligned pitch split for unidirectional metal wiring'20179,786,550'Low resistance metal contacts to interconnects'20179,728,421'High aspect ratio patterning of hard mask materials by organic soft masks'20179,711,365'Etch rate enhancement for a silicon etch process through etch chamber pretreatment'20179,705,077'Spin torque MRAM fabrication using negative tone lithography and ion beam etching'20179,691,972'Low temperature encapsulation for magnetic tunnel junction'20179,653,395'Hybrid subtractive etch/metal fill process for fabricating interconnects'20179,646,881'Hybrid subtractive etch/metal fill process for fabricating interconnects'20179,583,401'Nano deposition and ablation for the repair and fabrication of integrated circuits'20179,564,362'Interconnects based on subtractive etching of silver'20179,536,731'Wet clean process for removing CxHyFz etch residue'20179,493,879'Selective sputtering for pattern transfer'20169,484,220'Sputter etch processing for heavy metal patterning in integrated circuits'20169,472,499'Self-aligned pitch split for unidirectional metal wiring'20169,299,638'Patterning transition metals in integrated circuits'20169,299,639'Patterning transition metals in integrated circuits'20169,263,393'Sputter and surface modification etch processing for metal patterning in integrated circuits'20169,171,796'Sidewall image transfer for heavy metal patterning in integrated circuits'20159,166,165'Uniform critical dimension size pore for PCRAM application'20159,114,438'Copper residue chamber clean'20159,105,583'Catalytic etch with magnetic direction control'20159,064,727'Sputter and surface modification etch processing for metal patterning in integrated circuits'20159,018,090'Borderless self-aligned metal contact patterning using printable dielectric materials'20159,013,010'Nanopore sensor device'20158,993,907'Silicide micromechanical device and methods to fabricate same'20158,987,031'Fabricating a small-scale radiation detector'20158,928,124'High aspect ratio and reduced undercut trench etch process for a semiconductor substrate'20158,900,975'Nanopore sensor device'20148,884,387'Pillar-based interconnects for magnetoresistive random access memory'20148,871,107'Subtractive plasma etching of a blanket layer of metal or metal alloy'20148,809,828'Small footprint phase change memory cell'20148,796,041'Pillar-based interconnects for magnetoresistive random access memory'20148,772,906'Thermally insulated phase change material cells'20148,728,859'Small footprint phase change memory cell'20148,686,391'Pore phase change material cell fabricated from recessed pillar'20148,652,969'High aspect ratio and reduced undercut trench etch process for a semiconductor substrate'20148,633,464'In via formed phase change memory cell with recessed pillar heater'20148,633,117'Sputter and surface modification etch processing for metal patterning in integrated circuits'20148,536,675'Thermally insulated phase change material memory cells'20138,518,718'Magnetic spin shift register memory'20138,471,236'Flat lower bottom electrode for phase change memory cell'20138,470,628'Methods to fabricate silicide micromechanical device'20138,467,221'Magnetic spin shift register memory'20138,466,006'Thermally insulated phase material cells'20138,445,313'Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process'20138,431,486'Interconnect structure for improved time dependent dielectric breakdown'20138,426,967'Scaled-down phase change memory cell in recessed heater'20138,344,351'Phase change memory device with plated phase change material'20138,338,225'Method to reduce a via area in a phase change memory cell'20128,330,137'Pore phase change material cell fabricated from recessed pillar'20128,288,236'Field effect transistor having nanostructure channel'20128,283,650'Flat lower bottom electrode for phase change memory cell'20128,273,598'Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process'20128,232,171'Structure with isotropic silicon recess profile in nanoscale dimensions'20128,189,372'Integrated circuit including electrode having recessed portion'20128,138,056'Thermally insulated phase change material memory cells with pillar structure'20128,138,028'Method for manufacturing a phase change memory device with pillar bottom electrode'20128,119,528'Nanoscale electrodes for phase change memory devices'20128,115,186'Phase change memory cell with reduced switchable volume'20128,105,859'In via formed phase change memory cell with recessed pillar heater'20128,101,456'Method to reduce a via area in a phase change memory cell'20128,030,130'Phase change memory device with plated phase change material'20117,981,755'Self aligned ring electrodes'20117,972,966'Etching of tungsten selective to titanium nitride'20117,960,203'Pore phase change material cell fabricated from recessed pillar'20117,910,911'Phase change memory with tapered heater'20117,906,368'Phase change memory with tapered heater'20117,851,323'Phase change material with filament electrode'20107,834,339'Programmable-resistance memory cell'20107,755,921'Method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices'20107,709,325'Method of forming ring electrode'20107,560,721'Phase change material with filament electrode'20097,485,487'Phase change memory cell with electrode'20096,803,661'Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography'20046,624,068'Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2004Based in Dallas, TX, US· patent location history
2009–2020Patents assigned to IBM (87)· patent assignee history
2009–2020Based in White Plains, NY, US· patent location history
2011–2012Based in Yorktown Heights, NY, US· patent location history
2012–2015Patents assigned to JOSEPH ERIC A (25)· patent assignee history
2012–2014Patents assigned to BREITWISCH MATTHEW J (18)· patent assignee history
2012–2014Patents assigned to SCHROTT ALEJANDRO G (15)· patent assignee history
2012–2014Patents assigned to LAM CHUNG H (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM872009–2020
JOSEPH ERIC Aself252012–2015
BREITWISCH MATTHEW J182012–2014
SCHROTT ALEJANDRO G152012–2014
LAM CHUNG H132012–2014
Locations
LocationPatentsSpan
White Plains, New York, US892009–2020
Yorktown Heights, New York, US22011–2012
Dallas, Texas, US22003–2004