Inventor
Fong Pong
Inventor
Mountain View, CA, US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing62%
H04LTransmission of digital information, e.g. telegraphic communication28%
G11CStatic stores3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
9,344,377'Packet processing architecture'20169,304,944'Secure memory access controller'20168,812,795'Shared memory architecture'20148,718,065'Transmission using multiple physical interface'20148,619,790'Adaptive cache for caching context and for adapting to collisions in a session lookup table'20138,427,945'SoC device with integrated supports for Ethernet, TCP, iSCSI, RDMA and network application acceleration'20138,281,081'Shared memory architecture'20128,185,710'Hardware memory locks'20128,166,127'Apparatus and methods for efficient insertion and removal of MPA markers and RDMA CRC digest'20128,024,528'Global address space management'20118,001,333'Memory management in a shared memory system'20117,941,613'Shared memory architecture'20117,904,624'High bandwidth split bus'20117,885,268'Method and system for hash table based routing via table and prefix aggregation'20117,861,055'Method and system for on-chip configurable data ram for fast memory and pseudo associative caches'20107,852,851'Method and system for hash table based routing via a prefix transformation'20107,711,902'Area effective cache with pseudo associative memory'20107,698,523'Hardware memory locks'20107,653,070'Method and system for supporting efficient and cache-friendly TCP session lookup operations based on canonicalization tags'20107,636,816'Global address space management'20097,631,150'Memory management in a shared memory system'20097,596,144'System-on-a-chip (SoC) device with integrated support for ethernet, TCP, iSCSI, RDMA, and network application acceleration'20097,571,259'Apparatus and methods for efficient insertion and removal of MPA markers and RDMA CRC digest'20097,564,854'Network architecture with a light-weight TCP stack'20097,500,031'Ring-based cache coherent bus'20097,475,176'High bandwidth split bus'20097,274,706'Methods and systems for processing network data'20077,120,752'Multi-processor computer system with cache-flushing system using memory recall'20066,976,205'Method and apparatus for calculating TCP and UDP checksums while preserving CPU resources'20056,880,045'Multi-processor computer system with transactional memory'20056,874,065'Cache-flushing engine for distributed shared memory multi-processor computer systems'20056,851,074'System and method for recovering from memory failures in computer systems'20056,745,294'Multi-processor computer system with lock driven cache-flushing system'20046,728,843'System and method for tracking and processing parallel coherent memory accesses'20046,675,262'Multi-processor computer system with cache-flushing system using memory recall'20046,654,854'Caching method using cache tag and cache data stored in dynamic RAM embedded in logic chip'20036,516,343'Computer system and method for enhancing memory-to-memory copy transactions by utilizing multiple system control units'20036,490,662'System and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module'20026,449,690'Caching method using cache data stored in dynamic RAM embedded in logic chip and cache tag stored in static RAM external to logic chip'20026,360,231'Transactional memory for distributed shared memory multi-processor computer systems'20026,341,337'Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic'20026,253,291'Method and apparatus for relaxing the FIFO ordering constraint for memory accesses in a multi-processor asynchronous cache system'20016,199,142'Processor/memory device with integrated CPU, main memory, and full width cache and associated method'20016,128,702'Integrated processor/memory device with victim data cache'20006,119,205'Speculative cache line write backs to avoid hotspots'20006,073,212'Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags'20005,909,697'Reducing cache misses by snarfing writebacks in non-inclusive memory systems'19995,900,011'Integrated processor/memory device with victim data cache'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2002Patents assigned to SUN MICROSYSTEMS INC (8)· patent assignee history
1999–2016Based in Mountain View, CA, US· patent location history
2002Patents assigned to HEWLETT PACKARD CO (3)· patent assignee history
2003–2006Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (7)· patent assignee history
2009–2016Patents assigned to BROADCOM CORP (26)· patent assignee history
2012–2016Patents assigned to PONG FONG (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| BROADCOM CORP | 26 | 2009–2016 |
| PONG FONGself | 9 | 2012–2016 |
| SUN MICROSYSTEMS INC | 8 | 1999–2002 |
| HEWLETT PACKARD DEVELOPMENT CO | 7 | 2003–2006 |
| HEWLETT PACKARD CO | 3 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 48 | 1999–2016 |