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Inventor

Darren S. Jue

Inventor
Sunnyvale, CA, US

Overview

29→
Patents
2003–2021
Patent span
Physics
Primary field (CPC G)

Patents· 29 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing42%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use23%
H04LTransmission of digital information, e.g. telegraphic communication22%
G06NComputing arrangements based on specific computational models12%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
11,080,212High performance interconnect physical layer202110,983,920Customizable multi queue DMA interface202110,909,055High performance interconnect physical layer202110,795,841High performance interconnect physical layer202010,657,084Interrupt moderation and aggregation circuitry202010,606,774High performance interconnect physical layer202010,387,339High performance interconnect physical layer201910,380,046High performance interconnect physical layer201910,248,591High performance interconnect201910,216,674High performance interconnect physical layer201910,216,661High performance interconnect physical layer201910,146,733High performance interconnect physical layer201810,002,095High performance interconnect physical layer20189,916,266'High performance interconnect physical layer'20189,892,086'High performance interconnect physical layer'20189,697,158'High performance interconnect physical layer'20179,626,321'High performance interconnect'20179,612,986'High performance interconnect physical layer'20179,600,431'High performance interconnect physical layer'20179,418,035'High performance interconnect physical layer'20169,378,171'High performance interconnect physical layer'20169,355,058'High performance interconnect physical layer'20169,280,507'High performance interconnect physical layer'20169,229,897'Embedded control channel for high speed serial interconnect'20169,208,121'High performance interconnect physical layer'20159,183,171'Fast deskew when exiting low-power partial-width high speed link state'20159,104,793'Method and system of adapting communication links to link conditions on a platform'20156,775,814'Dynamic system configuration for functional design verification'20046,611,936'Programmable delay elements for source synchronous link function design verification through simulation'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2021Based in Sunnyvale, CA, US· patent location history
2015–2021Patents assigned to INTEL CORP (25)· patent assignee history
2015–2016Patents assigned to IYER VENKATRAMAN (2)· patent assignee history
2015–2016Patents assigned to JUE DARREN S (2)· patent assignee history
2016Patents assigned to BLANKENSHIP ROBERT G (1)· patent assignee history
2020–2021Patents assigned to XILINX INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP252015–2021
IYER VENKATRAMAN22015–2016
JUE DARREN Sself22015–2016
XILINX INC22020–2021
BLANKENSHIP ROBERT G12016
Locations
LocationPatentsSpan
Sunnyvale, California, US292003–2021