Inventor

Thomas R. Wik

Inventor
Livermore, CA, US

Overview

24→
Patents
1996–2017
Patent span
Physics
Primary field (CPC G)

Patents· 24 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores43%
G06FElectric digital data processing11%
H03KPulse technique11%
F24SSolar heat collectors6%
H02SGeneration of electric power by conversion of infrared radiation, visible light or ultraviolet light, e.g. using photovoltaic [pv] modules6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation6%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution6%
F24J3%
H01LSemiconductor devices3%
H03MCoding3%
PatentTitleYear
9,780,722'Low-cost efficient solar panels'20179,762,261'Error detection and correction in ternary content addressable memory (TCAM)'20179,529,669'Error detection and correction in binary content addressable memory (BCAM)'20168,921,680'Low-cost solar collector'20147,746,921'Resonant digital data transmission'20107,603,509'Crossbar switch with grouped inputs and outputs'20097,557,618'Conditioning logic technology'20096,507,524'Integrated circuit memory having column redundancy'20036,370,078'Way to compensate the effect of coupling between bitlines in a multi-port memories'20026,233,197'Multi-port semiconductor memory and compiler having capacitance compensation'20016,137,716'Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell'20006,018,480'Method and system which permits logic signal routing over on-chip memories'20005,987,632'Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations'19995,982,659'Memory cell capable of storing more than two logic states by using different via resistances'19995,903,505'Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions'19995,867,423'Memory circuit and method for multivalued logic storage by process variations'19995,847,990'Ram cell capable of storing 3 logic states'19985,841,695'Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell'19985,808,932'Memory system which enables storage and retrieval of more than two states in a memory cell'19985,796,650'Memory circuit including write control unit wherein subthreshold leakage may be reduced'19985,784,328'Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array'19985,761,110'Memory cell capable of storing more than two logic states by using programmable resistances'19985,559,463'Low power clock circuit'19965,506,519'Low energy differential logic gate circuitry having substantially invariant clock signal loading'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996Patents assigned to AT & T CORP (1)· patent assignee history
1996Based in Hanover Township, PA, US· patent location history
1996Based in Bethlehem Township, Northampton County, PA, US· patent location history
1998–2003Patents assigned to LSI LOGIC CORP (15)· patent assignee history
1998–2017Based in Livermore, CA, US· patent location history
2009Patents assigned to ADAPTIVE DESIGN SOLUTIONS INC (1)· patent assignee history
2010–2017Patents assigned to WIK THOMAS ROBERT (3)· patent assignee history
2016–2017Patents assigned to ESILICON CORP (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI LOGIC CORP151998–2003
WIK THOMAS ROBERTself32010–2017
ESILICON CORP22016–2017
ADAPTIVE DESIGN SOLUTIONS INC12009
AT & T CORP11996
Locations
LocationPatentsSpan
Livermore, California, US221998–2017
Hanover Township, Pennsylvania, US11996
Bethlehem Township, Northampton County, Pennsylvania, US11996