Inventor
MAURO KOBRINSKY
Inventor
US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
B82YSpecific uses or applications of nanostructures7%
H10BElectronic memory devices4%
H05KPrinted circuits3%
G11CStatic stores1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,598,977Fill of vias in single and dual damascene structures using self-assembled monolayer202612,513,984Double-sided integrated circuit transistor structures with depopulated bottom channel regions202512,506,075Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner202512,506,059Vertically spaced intra-level interconnect line metallization for integrated circuit devices202512,426,342Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability202512,394,716Integrated circuit interconnect structures with graphene cap202512,342,574Contact resistance reduction in transistor devices with metallization on both sides202512,334,392Multi-height interconnect trenches for resistance and capacitance optimization202512,315,794Skip level vias in metallization layers for integrated circuit devices202512,288,746Skip level vias in metallization layers for integrated circuit devices202512,211,794Integrated circuits and methods for forming thin film crystal layers202512,199,143Gate-all-around integrated circuit structures having removed substrate202512,107,170Transistor channel passivation with 2D crystalline material202411,985,909Fabrication of stackable embedded eDRAM using a binary alloy based on antimony202411,948,874Vertically spaced intra-level interconnect line metallization for integrated circuit devices202411,830,788Integrated circuits and methods for forming integrated circuits202311,721,554Stress compensation for wafer to wafer bonding202311,532,558Metallization barrier structures for bonded integrated circuit interfaces202211,410,928Device layer interconnects202211,276,644Integrated circuits and methods for forming thin film crystal layers202211,189,585Selective recess of interconnects for probing hybrid bond devices202111,164,809Integrated circuits and methods for forming integrated circuits2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (22)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 22 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 22 | 2021–2026 |