Inventor
Ying Yu TAI
Inventor
US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing62%
G11CStatic stores29%
H03MCoding5%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
12,561,072Corrective read with parallel auto-read calibration in a memory sub-system202612,436,702Hybrid wear leveling for in-place data replacement media202512,423,027Enabling multiple data capacity modes at a memory sub-system202512,314,193Scheduling of read operations and write operations based on a data bus mode202512,189,960Limiting hot-cold swap wear leveling202512,182,318Cryptographic key management202412,164,769Adaptive media management for memory systems202412,147,689Temperature-based media management for memory components202412,135,876Memory systems having controllers embedded in packages of integrated circuit memory202412,039,196Double threshold controlled scheduling of memory access commands202411,907,563Clock domain crossing queue202411,874,779Scheduling of read operations and write operations based on a data bus mode202411,874,769Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations202411,869,618Memory sub-system including an in-package sequencer to perform error correction and memory testing operations202411,861,167Maintenance operations for memory devices202411,782,606Scanning techniques for a media-management operation of a memory sub-system202311,768,615Temperature-based media management for memory components202311,733,925Enabling multiple data capacity modes at a memory sub-system202311,726,815Scheduling command execution202311,714,697Reset and replay of memory sub-system controller in a memory sub-system202311,709,733Metadata-assisted encoding and decoding for a memory sub-system202311,704,024Multi-level wear leveling for non-volatile memory202311,687,363Internal management traffic regulation for memory sub-systems202311,681,472Unmap data pattern for coarse mapping memory sub-system202311,681,442Performing hybrid wear leveling operations based on a sub-total write counter202311,675,714Memory sub-system including an in package sequencer separate from a controller202311,669,275Controller with distributed sequencer components202311,632,137Early decoding termination for a memory sub-system202311,620,085Management of write operations in a non-volatile memory device using a variable pre-read voltage level202311,615,214Cryptographic key management202311,587,628Refreshing data stored at a memory component based on a memory component characteristic component202311,567,817Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller202311,550,663Changing of error correction codes based on the wear of a memory sub-system202311,537,307Hybrid wear leveling for in-place data replacement media202211,526,395Write buffer management202211,481,119Limiting hot-cold swap wear leveling202211,461,030Transferring data between clock domains using pulses across a queue202211,404,092Cross point array memory in a non-volatile dual in-line memory module202211,392,292Maintenance operations for memory devices202211,360,672Performing hybrid wear leveling operations based on a sub-total write counter202211,341,036Biased sampling methodology for wear leveling202211,320,987Scanning techniques for a media-management operation of a memory sub-system202211,307,983Maintaining data consistency in a memory subsystem that uses hybrid wear leveling operations202211,294,750Media management logger for a memory sub-system202211,288,013Hardware based status collector acceleration engine for memory sub-system operations202211,281,533Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems202211,243,831Reset and replay of memory sub-system controller in a memory sub-system202211,216,218Unmap data pattern for coarse mapping memory sub-system202211,199,999Management of write operations in a non-volatile memory device using a variable pre-read voltage level202111,164,641Refreshing data stored at a memory component based on a memory component characteristic component2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (50)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 50 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 50 | 2021–2026 |