Inventor

Hoichi Cheong

Inventor

Austin, TX, US

Overview

36→

Patents

1996–2017

Patent span

Physics

Primary field (CPC G)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing95%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

PatentTitleYear

9,710,277'Processor power management based on class and content of instructions'2017 8,930,678'Instruction and logic to length decode X86 instructions'2015 7,783,871'Method to remove stale branch predictions for an instruction prior to execution within a microprocessor'2010 7,266,648'Cache lock mechanism with speculative allocation'2007 7,080,241'Mechanism for self-initiated instruction issuing and method therefor'2006 6,986,010'Cache lock mechanism with speculative allocation'2006 6,898,696'Method and system for efficiently restoring a processor\'s execution state following an interrupt caused by an interruptible instruction'2005 6,604,173'System for controlling access to external cache memories of differing size'2003 6,553,480'System and method for managing the execution of instruction groups having multiple executable instructions'2003 6,535,973'Method and system for speculatively issuing instructions'2003 6,473,850'System and method for handling instructions occurring after an ISYNC instruction'2002 6,324,640'System and method for dispatching groups of instructions using pipelined register renaming'2001 6,308,260'Mechanism for self-initiated instruction issuing and method therefor'2001 6,098,167'Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution'2000 6,073,211'Method and system for memory updates within a multiprocessor data processing system'2000 6,070,235'Data processing system and method for capturing history buffer data'2000 6,061,777'Apparatus and method for reducing the number of rename registers required in the operation of a processor'2000 5,996,085'Concurrent execution of machine context synchronization operations and non-interruptible instructions'1999 5,983,341'Data processing system and method for extending the time for execution of an instruction'1999 5,974,524'Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution'1999 5,961,636'Checkpoint table for selective instruction flushing in a speculative execution unit'1999 5,913,048'Dispatching instructions in a processor supporting out-of-order execution'1999 5,897,651'Information handling system including a direct access set associative cache and method for accessing same'1999 5,887,161'Issuing instructions in a processor supporting out-of-order execution'1999 5,875,326'Data processing system and method for completing out-of-order instructions'1999 5,870,582'Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched'1999 5,870,612'Method and apparatus for condensed history buffer'1999 5,860,014'Method and apparatus for improved recovery of processor state using history buffer'1999 5,822,752'Method and apparatus for fast parallel determination of queue entries'1998 5,805,906'Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions'1998 5,774,712'Instruction dispatch unit and method for mapping a sending order of operations to a receiving order'1998 5,754,885'Apparatus and method for selecting entries from an array'1998 5,694,573'Shared L2 support for inclusion property in split L1 data and instruction caches'1997 5,692,151'High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address'1997 5,584,013'Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache'1996 5,533,189'System and method for error correction code generation'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2006Patents assigned to IBM (31)· patent assignee history

1996–2017Based in Austin, TX, US· patent location history

1997Based in Travis, TX, US· patent location history

2006–2017Patents assigned to INTEL CORP (5)· patent assignee history

2015–2017Patents assigned to CHEONG HOICHI (2)· patent assignee history

2015–2017Patents assigned to MADDURI VENKATESWARA R (2)· patent assignee history

2015–2017Patents assigned to TONG JONATHAN Y (2)· patent assignee history

2015Based in Atlit, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	31	1996–2006
INTEL CORP	5	2006–2017
CHEONG HOICHIself	2	2015–2017
MADDURI VENKATESWARA R	2	2015–2017
TONG JONATHAN Y	2	2015–2017

Locations

Location	Patents	Span
Austin, Texas, US	34	1996–2017
Atlit, Texas, US	1	2015
Travis, Texas, US	1	1997