LexDanaLexDanabeta
Inventor

Franz Hofmann

Inventor
Munich, DE

Overview

128→
Patents
1978–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 128 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices37%
H10DInorganic electric semiconductor devices27%
G11CStatic stores8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H10KOrganic electric solid-state devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
B82YSpecific uses or applications of nanostructures2%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
B22CFoundry moulding1%
H01LSemiconductor devices1%
PatentTitleYear
10,970,484Method and system for providing encoded communication between users of a network202110,186,515Antifuse cell comprising program transistor and select transistor arranged on opposite sides of semiconductor layer20199,956,712Method for producing a pressure accumulator, and pressure accumulator20189,816,668'Device for storing and delivery of a liquid and/or gaseous medium under pressure, as well as a fuel energy conversion device and method for assembling a device for storing and delivery of a liquid and/or gaseous medium under pressure'20179,640,664'SOI finfet with reduced fin width dependence'20179,472,469'Back gate in select transistor for eDRAM'20168,702,921'Biosensors array and method for operating a biosensor array'20148,492,844'Fully depleted SOI device with buried doped layer'20138,480,877'Sensor arrangement comprising an electrode for detecting diffused loaded particles'20138,258,564'Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method'20128,241,989'Integrated circuit with stacked devices'20128,097,915'Semiconductor memory device'20128,067,249'Method for functionalizing biosensor chips'20117,915,667'Integrated circuits having a contact region and methods for manufacturing the same'20117,893,519'Integrated circuit with conductive structures'20117,838,925'Integrated circuit including a vertical transistor and method'20107,829,892'Integrated circuit including a gate electrode'20107,778,073'Integrated circuit having NAND memory cell strings'20107,772,580'Integrated circuit having a cell with a resistivity changing layer'20107,767,567'Method of forming a semiconductor memory device and semiconductor memory device'20107,719,059'Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement'20107,714,377'Integrated circuits and methods of manufacturing thereof'20107,709,827'Vertically integrated field-effect transistor having a nanostructure therein'20107,700,427'Integrated circuit having a Fin structure'20107,692,246'Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement'20107,635,867'Nanotube array and method for producing a nanotube array'20097,611,928'Method for producing a substrate'20097,598,543'Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration'20097,560,351'Integrated circuit arrangement with low-resistance contacts and method for production thereof'20097,528,425'Semiconductor memory with charge-trapping stack arrangement'2009RE040532'Non-volatile memory cell and fabrication method'20087,411,822'Nonvolatile memory cell arrangement'20087,400,695'System and method for time-marking data'20087,385,243'Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating gate memory gate cell'20087,368,752'DRAM memory cell'20087,352,018'Non-volatile memory cells and methods for fabricating non-volatile memory cells'20087,344,923'NROM semiconductor memory device and fabrication method'20087,335,939'Semiconductor memory device and method of production'20087,307,865'Integrated read-only memory, method for operating said read-only memory and corresponding production method'20077,298,004'Charge-trapping memory cell and method for production'20077,265,424'Fin Field-effect transistor and method for producing a fin field effect-transistor'20077,265,413'Semiconductor memory with vertical memory transistors and method for fabricating it'20077,265,376'Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell'20077,214,582'Semiconductor substrate and semiconductor circuit formed therein and fabrication methods'20077,208,794'High-density NROM-FINFET'20077,195,978'Method for the production of a memory cell, memory cell and memory cell arrangement'20077,180,115'DRAM cell structure with tunnel barrier'20077,157,767'Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory element and method for operating a semiconductor memory element'20077,157,768'Non-volatile flash semiconductor memory and fabrication method'20077,154,138'Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement'20067,075,148'Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells'20067,060,558'Method for fabricating a field-effect transistor having a floating gate'20067,034,371'Biochip for the capacitive stimulation and/or detection of biological tissue and a method for its production'20067,030,434'Arrangement with image sensors'20066,998,672'Memory cell'20066,982,202'Fabrication method for memory cell'20066,979,859'Flash memory cell and fabrication method'20056,977,413'Bar-type field effect transistor and method for the production thereof'20056,960,505'Method for manufacturing a multi-bit memory cell'20056,914,292'Floating gate field-effect transistor'20056,900,495'Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement'20056,798,014'Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore'20046,750,095'Integrated circuit with vertical transistors'20046,734,063'Non-volatile memory cell and fabrication method'20046,730,930'Memory element and method for fabricating a memory element'20046,707,098'Electronic device and method for fabricating an electronic device'20046,673,677'Method for manufacturing a multi-bit memory cell'20046,639,269'Electrically programmable memory cell configuration and method for fabricating it'20036,638,812'Method for producing a memory cell for a semiconductor memory'20036,608,340'Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication'20036,599,797'SOI DRAM without floating body effect'20036,593,614'Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it'20036,576,948'Integrated circuit configuration and method for manufacturing it'20036,566,182'DRAM memory cell for DRAM memory device and method for manufacturing it'20036,566,193'Method for producing a cell of a semiconductor memory'20036,534,820'Integrated dynamic memory cell having a small area of extent, and a method for its production'20036,518,628'Integrated CMOS circuit configuration, and production of same'20036,492,221'DRAM cell arrangement'20026,475,866'Method for production of a memory cell arrangement'20026,469,335'Semiconductor memory having a memory cell array'20026,448,600'DRAM cell configuration and fabrication method'20026,445,046'Memory cell arrangement and process for manufacturing the same'20026,442,065'Method for operating a memory cell configuration having dynamic gain memory cells'20026,438,022'Memory cell configuration'20026,420,228'Method for the production of a DRAM cell configuration'20026,399,433'Method for fabricating a memory cell'20026,362,502'DRAM cell circuit'20026,352,894'Method of forming DRAM cell arrangement'20026,349,052'DRAM cell arrangement and method for fabricating it'20026,316,315'Method for fabricating a memory cell having a MOS transistor'20016,300,652'Memory cell configuration and method for its production'20016,274,453'Memory cell configuration and production process therefor'20016,265,748'Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement'20016,255,684'DRAM cell configuration and method for its production'20016,242,319'Method for fabricating an integrated circuit configuration'20016,229,169'Memory cell configuration, method for fabricating it and methods for operating it'20016,191,459'Electrically programmable memory cell array, using charge carrier traps and insulation trenches'20016,180,979'Memory cell arrangement with vertical MOS transistors and the production process thereof'20016,180,458'Method of producing a memory cell configuration'20016,153,475'Method for the manufacturing a memory cell configuration'20006,125,050'Configuration for driving parallel lines in a memory cell configuration'20006,118,159'Electrically programmable memory cell configuration'20006,111,267'CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer'20006,064,101'Read-only memory cell arrangement'20006,049,105'DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing same'20006,044,009'DRAM cell arrangement and method for its production'20006,040,995'Method of operating a storage cell arrangement'20006,037,209'Method for producing a DRAM cellular arrangement'20005,998,261'Method of producing a read-only storage cell arrangement'19995,994,746'Memory cell configuration and method for its fabrication'19995,973,373'Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production'19995,959,328'Electrically programmable memory cell arrangement and method for its manufacture'19995,920,778'Read-only memory cell arrangement and method for its production'19995,920,099'Read-only memory cell array and process for manufacturing it'19995,882,969'Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement'19995,821,591'High density read only memory cell configuration and method for its production'19985,744,393'Method for production of a read-only-memory cell arrangement having vertical MOS transistors'19985,736,761'DRAM cell arrangement and method for its manufacture'19985,710,072'Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells'19985,559,353'Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof'19965,443,992'Method for manufacturing an integrated circuit having at least one MOS transistor'19955,432,115'Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench'19955,385,852'Method for manufacturing vertical MOS transistors'19954,964,668'Top for vehicles, particularly passenger cars'19904,713,180'Ceramic filter and method for using same'19874,274,360'Apparatus for regenerating used foundry sand'19814,231,984'Process for the production of molded phosphate bonded refractory articles'19804,113,238'Drum mixer'1978

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1978–1987Patents assigned to FISCHER AG GEORG (4)· patent assignee history
1978–1987Based in Neuhausen, CH· patent location history
1995–2014Patents assigned to SIEMENS AG (35)· patent assignee history
1995–2019Based in Munich, DE· patent location history
2001–2010Patents assigned to INFINEON TECHNOLOGIES AG (62)· patent assignee history
2002–2004Based in Mnchen, DE· patent location history
2005–2013Based in München, DE· patent location history
2009–2012Patents assigned to QIMONDA AG (14)· patent assignee history
2011–2014Patents assigned to HOFMANN FRANZ (7)· patent assignee history
2021Based in Wiesbaden, DE· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INFINEON TECHNOLOGIES AG622001–2010
SIEMENS AG351995–2014
QIMONDA AG142009–2012
HOFMANN FRANZself72011–2014
FISCHER AG GEORG41978–1987
Locations
LocationPatentsSpan
Munich, DE731995–2019
München, DE232005–2013
Mnchen, DE202002–2004
Neuhausen, CH41978–1987
Wiesbaden, DE12021