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Inventor

Yaron Kretchmer

Inventor
Fremont, CA, US

Overview

5→
Patents
2005–2012
Patent span
Physics
Primary field (CPC G)

Patents· 5 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing40%
G11CStatic stores40%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
PatentTitleYear
8,099,692'Power-driven timing analysis and placement for programmable logic'20127,861,190'Power-driven timing analysis and placement for programmable logic'20107,365,413'Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern'20087,139,991'Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs'20066,931,606'Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2006Patents assigned to LSI LOGIC CORP (2)· patent assignee history
2005–2012Based in Fremont, CA, US· patent location history
2008–2012Patents assigned to ALTERA CORP (3)· patent assignee history
2012Patents assigned to BETZ VAUGHN (1)· patent assignee history
2012Patents assigned to KRETCHMER YARON (1)· patent assignee history
2012Patents assigned to LEVENTIS PAUL (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP32008–2012
LSI LOGIC CORP22005–2006
BETZ VAUGHN12012
KRETCHMER YARONself12012
LEVENTIS PAUL12012
Locations
LocationPatentsSpan
Fremont, California, US52005–2012