Inventor
Darvin R. Edwards
Inventor
Garland, TX, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H01LSemiconductor devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H05KPrinted circuits8%
G06FElectric digital data processing6%
Y10TTechnical subjects covered by former us classification6%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form4%
G01RMeasuring electric variables4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
B23KSoldering or unsoldering2%
PatentTitleYear
9,698,075'Integration of backside heat spreader for thermal management'20179,496,198'Integration of backside heat spreader for thermal management'20169,373,572'Semiconductor package having etched foil capacitor integrated into leadframe'20169,165,873'Semiconductor package having etched foil capacitor integrated into leadframe'20159,142,496'Semiconductor package having etched foil capacitor integrated into leadframe'20158,716,068'Method for contacting agglomerate terminals of semiconductor packages'20148,643,165'Semiconductor device having agglomerate terminals'20147,892,889'Array-processed stacked semiconductor packages'20117,495,749'Rapid method for sub-critical fatigue crack growth evaluation'20097,296,168'Method and apparatus to minimize power and ground bounce in a logic device'20077,291,913'System and method for high performance heat sink for multiple chip devices'20077,267,861'Solder joints for copper metallization having reduced interfacial voids'20077,174,194'Temperature field controlled scheduling for processing systems'20076,979,899'System and method for high performance heat sink for multiple chip devices'20056,950,310'System and method for self-leveling heat sink for multiple height devices'20056,730,541'Wafer-scale assembly of chip-size packages'20046,586,839'Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers'20036,450,397'Method of making ball grid array columns'20026,365,958'Sacrificial structures for arresting insulator cracks in semiconductor devices'20026,080,650'Method and apparatus for attaching particles to a substrate'20006,064,576'Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board'20005,604,687'Thermal analysis system and method of operation'19975,579,249'System for modeling an integrated chip package and method of operation'19965,466,888'Packaged semiconductor device having stress absorbing film'19955,406,028'Packaged semiconductor device having stress absorbing film'19955,321,277'Multi-chip module testing'19945,083,187'Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2017Patents assigned to TEXAS INSTRUMENTS INC (27)· patent assignee history
1992–1995Based in Dallas, TX, US· patent location history
1995Patents assigned to HITACHI LTD (2)· patent assignee history
1996–2017Based in Garland, TX, US· patent location history
2014Patents assigned to EDWARDS DARVIN R (1)· patent assignee history
2014Patents assigned to GURRUM SIVA PRAKASH (1)· patent assignee history
2014Patents assigned to HAYATA KAZUNORI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 27 | 1992–2017 |
| HITACHI LTD | 2 | 1995 |
| EDWARDS DARVIN Rself | 1 | 2014 |
| GURRUM SIVA PRAKASH | 1 | 2014 |
| HAYATA KAZUNORI | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Garland, Texas, US | 23 | 1996–2017 |
| Dallas, Texas, US | 4 | 1992–1995 |