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Inventor

Kunio Uchiyama

Inventor
Kodaira, JP

Overview

73→
Patents
1987–2013
Patent span
Physics
Primary field (CPC G)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing40%
G11CStatic stores21%
H10DInorganic electric semiconductor devices14%
H03KPulse technique10%
H04NPictorial communication, e.g. television6%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H10BElectronic memory devices2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%
PatentTitleYear
8,364,988'Substrate bias switching unit for a low power processor'20138,234,441'Processor system using synchronous dynamic memory'20127,958,379'Substrate bias switching unit for a low power processor'20117,904,641'Processor system using synchronous dynamic memory'20117,750,668'Semiconductor integrated circuit device having power reduction mechanism'20107,475,261'Substrate bias switching unit for a low power processor'20097,376,783'Processor system using synchronous dynamic memory'20087,312,640'Semiconductor integrated circuit device having power reduction mechanism'20077,254,082'Semiconductor device'20077,162,616'Floating point unit pipeline synchronized with processor pipeline'20077,143,230'Processor system using synchronous dynamic memory'20067,023,757'Semiconductor device'20066,970,019'Semiconductor integrated circuit device having power reduction mechanism'20056,879,188'Semiconductor integrated circuit device'20056,779,102'Data processor capable of executing an instruction that makes a cache memory ineffective'20046,772,327'Floating point unit pipeline synchronized with processor pipeline'20046,753,231'Semiconductor integrated circuit and method for manufacturing the same'20046,715,090'Processor for controlling substrate biases in accordance to the operation modes of the processor'20046,696,865'Semiconductor integrated circuit device having power reduction mechanism'20046,697,908'Processor system using synchronous dynamic memory'20046,601,218'Semiconductor integrated circuit device'20036,559,006'Semiconductor integrated circuit and method for manufacturing the same'20036,532,579'Semiconductor integrated circuit and design method and manufacturing method of the same'20036,532,528'Data processor and data processor system having multiple modes of address indexing and operation'20036,515,519'Semiconductor integrated circuit device'20036,504,402'Semiconductor integrated circuit device having power reduction mechanism'20036,436,741'Semiconductor integrated circuit device'20026,436,753'Semiconductor integrated circuit and method for manufacturing the same'20026,418,528'Floating point unit pipeline synchronized with processor pipeline'20026,404,239'Semiconductor integrated circuit device having power reduction mechanism'20026,356,119'Semiconductor integrated circuit device having power reduction mechanism'20026,334,166'Processor system using synchronous dynamic memory'20016,281,711'Semiconductor integrated circuit device having power reduction mechanism'20016,272,596'Data processor'20016,260,107'Processor system using synchronous dynamic memory'20016,175,251'Semiconductor integrated circuit device having power reduction'20016,107,836'Semiconductor integrated circuit device having power reduction mechanism'20006,092,172'Data processor and data processing system having two translation lookaside buffers'20006,078,986'Processor system using synchronous dynamic memory'20006,046,604'Semiconductor integrated circuit device having power reduction mechanism'20006,012,139'Microprocessor including floating point unit with 16-bit fixed length instruction set'20005,974,533'Data processor'19995,880,604'Semiconductor integrated circuit device having power reduction mechanism'19995,860,000'Floating point unit pipeline synchronized with processor pipeline'19995,828,235'Semiconductor integrated circuit device having power reduction mechanism'19985,809,274'Purge control for ON-chip cache memory'19985,680,631'Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory'19975,614,847'Semiconductor integrated circuit device having power reduction mechanism'19975,583,457'Semiconductor integrated circuit device having power reduction mechanism'19965,574,876'Processor system using synchronous dynamic memory'19965,555,394'Data processor with the ability of fast partial clearing of buffer memory'19965,454,087'Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT'19955,408,625'Microprocessor capable of decoding two instructions in parallel'19955,394,558'Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM'19955,386,394'Semiconductor memory device for performing parallel operations on hierarchical data lines'19955,349,672'Data processor having logical address memories and purge capabilities'19945,301,285'Data processor having two instruction registers connected in cascade and two instruction decoders'19945,287,484'Multi-processor system for invalidating hierarchical cache'19945,283,886'Multiprocessor cache system having three states for generating invalidating signals upon write accesses'19945,267,198'Static memory containing sense amp and sense amp switching circuit'19935,206,945'Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses'19935,202,969'Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively'19935,193,075'Static memory containing sense AMP and sense AMP switching circuit'19935,146,573'Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register'19925,140,681'Multi-processing system and cache apparatus for use in the same'19925,129,075'Data processor with on-chip logical addressing and off-chip physical addressing'19924,989,140'Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit'19914,937,738'Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction'19904,912,635'System for reexecuting branch instruction without fetching by storing target instruction control information'19904,803,616'Buffer memory'19894,797,816'Virtual memory supported processor having restoration circuit for register recovering'19894,720,811'Microprocessor capable of stopping its operation at any cycle time'19884,646,271'Content addressable memory having dual access modes'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2007Patents assigned to HITACHI LTD (54)· patent assignee history
1987–1990Based in Kokubunji, JP· patent location history
1988Based in Pittsburgh, PA, US· patent location history
1989–1999Patents assigned to HITACHI MICROCUMPUTER ENG (9)· patent assignee history
1989–2004Based in Hachioji, JP· patent location history
1992–1994Patents assigned to HITACHI VLSI ENG (5)· patent assignee history
1992–2013Based in Tokyo, JP· patent location history
1995–2012Based in Kodaira, JP· patent location history
1999–2004Patents assigned to HITACHI MICRO SYSTEMS INC (3)· patent assignee history
2004–2011Patents assigned to RENESAS TECH CORP (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HITACHI LTD541987–2007
RENESAS TECH CORP102004–2011
HITACHI MICROCUMPUTER ENG91989–1999
HITACHI VLSI ENG51992–1994
HITACHI MICRO SYSTEMS INC31999–2004
Locations
LocationPatentsSpan
Kodaira, JP431995–2012
Hachioji, JP171989–2004
Tokyo, JP101992–2013
Kokubunji, JP21987–1990
Pittsburgh, Pennsylvania, US11988