Inventor
Xavier Vera
Inventor
Barcelona, ES
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing51%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use21%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications11%
G11CStatic stores9%
H03MCoding4%
G01RMeasuring electric variables2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
10,528,473Disabling cache portions during low voltage operations202010,020,037Capacity register file20189,678,878'Disabling cache portions during low voltage operations'20179,619,309'Enforcing different operational configurations for different tasks for failure rate based control of processors'20179,608,922'Traffic control on an on-chip network'20179,405,647'Register error protection through binary translation'20169,286,172'Fault-aware mapping for shared last level cache (LLC)'20169,176,895'Increased error correction for cache memories through adaptive replacement policies'20159,170,947'Recovering from data errors using implicit redundancy'20159,112,537'Content-aware caches for reliability'20159,075,904'Vulnerability estimation for cache memory'20159,071,281'Selective provision of error correction for memory'20159,043,659'Banking of reliability metrics'20158,578,137'Reducing aging effect on registers'20138,477,558'Memory apparatuses with low supply voltages'20138,402,310'Detecting soft errors via selective re-execution'20138,352,812'Protecting data storage structures from intermittent errors'20138,291,168'Disabling cache portions during low voltage operations'20128,151,094'Dynamically estimating lifetime of a semiconductor device'20128,103,830'Disabling cache portions during low voltage operations'20128,090,996'Detecting soft errors via selective re-execution'20128,074,110'Enhancing reliability of a many-core processor'20118,069,376'On-line testing for decode logic'20117,747,913'Correcting intermittent errors in data storage structures'20107,689,804'Selectively protecting a register file'20107,600,145'Clustered variations-aware architecture'20097,577,015'Memory content inverting to minimize NTBI effects'20097,558,992'Reducing the soft error vulnerability of stored data'20097,447,054'NBTI-resilient memory cells with NAND gates'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to INTEL CORP (29)· patent assignee history
2008–2020Based in Barcelona, ES· patent location history
2011–2018Patents assigned to VERA XAVIER (17)· patent assignee history
2011–2018Patents assigned to ABELLA JAUME (12)· patent assignee history
2011–2018Patents assigned to CASADO JAVIER CARRETERO (10)· patent assignee history
2011–2017Patents assigned to GONZALEZ ANTONIO (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 29 | 2008–2020 |
| VERA XAVIERself | 17 | 2011–2018 |
| ABELLA JAUME | 12 | 2011–2018 |
| CASADO JAVIER CARRETERO | 10 | 2011–2018 |
| GONZALEZ ANTONIO | 10 | 2011–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Barcelona, ES | 29 | 2008–2020 |