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Inventor

Mitchell W. Hines

Inventor
San Jose, CA, US

Overview

6→
Patents
2005–2014
Patent span
Physics
Primary field (CPC G)

Patents· 6 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
8,683,419'Power domain crossing interface analysis'2014RE044479'Method and mechanism for implementing electronic designs having power information specifications background'20138,132,135'Method and system for creating a boolean model of multi-path and multi-strength signals for verification'20127,954,078'High level IC design with power specification and power source hierarchy'20117,735,035'Method and system for creating a boolean model of multi-path and multi-strength signals for verification'20106,848,084'Method and apparatus for verification of memories at multiple abstraction levels'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2014Patents assigned to CADENCE DESIGN SYSTEMS INC (6)· patent assignee history
2005–2014Based in San Jose, CA, US· patent location history
2013Patents assigned to BHATIA SANDEEP (1)· patent assignee history
2013Patents assigned to CHEN PINHONG (1)· patent assignee history
2013Patents assigned to CHEN YONGHOA (1)· patent assignee history
2013Patents assigned to CHICKERMANE VIVEK (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC62005–2014
BHATIA SANDEEP12013
CHEN PINHONG12013
CHEN YONGHOA12013
CHICKERMANE VIVEK12013
Locations
LocationPatentsSpan
San Jose, California, US62005–2014