Inventor
Jing Wang
Inventor
Beijing, CN
Overview
Patents· 61 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G06FElectric digital data processing5%
G01RMeasuring electric variables2%
H04WWireless communication networks2%
A61BDiagnosis2%
G06KGraphical data reading2%
G06NComputing arrangements based on specific computational models2%
PatentTitleYear
10,949,708Fine-grained image similarity202110,868,251Method for fabricating organic light emitting diode display202010,627,446Importance sampling method for multiple failure regions202010,621,494System and method for circuit simulation based on recurrent neural networks202010,469,996Group scan in overlapping geofences201910,388,750Semiconductor structure and method for forming the same201910,330,727Importance sampling method for multiple failure regions201910,204,188Systems, methods and computer program products for analyzing performance of semiconductor devices201910,163,042Finding missing persons by learning features for person attribute classification based on deep learning201810,146,896Method for transistor design with considerations of process, voltage and temperature variations201810,069,013Amplifiers including tunable tunnel field effect transistor pseudo resistors and related devices20189,728,639'Tunnel field effect transistors having low turn-on voltage'20179,526,436'Amplifiers including tunable tunnel field effect transistor pseudo resistors and related devices'20169,299,566'Method for forming germanium-based layer'20169,268,885'Integrated circuit device methods and models with predicted device metric variations'20169,159,814'Memory structure and method for forming same'20159,105,464'Semiconductor structure with rare earth oxide'20159,105,475'Method for forming fin field effect transistor'20159,059,268'Tunneling field effect transistor and method for fabricating the same'20159,041,126'Deeply depleted MOS transistors having a screening layer and methods thereof'20159,013,001'Stress-generating shallow trench isolation structure having dual composition'20159,006,088'Method for forming semiconductor gate structure and semiconductor gate structure'20158,963,295'Semiconductor structure with beryllium oxide'20158,927,966'Dynamic random access memory unit and method for fabricating the same'20158,890,209'Strained GE-ON-insulator structure and method for forming the same'20148,860,086'Semiconductor structure and method for forming the same'20148,860,143'High-K gate dielectric with work function adjustment metal layer'20148,860,140'Tunneling field effect transistor and method for forming the same'20148,853,674'Tunneling field effect transistor structure and method for forming the same'20148,815,690'Tunneling device and method for forming the same'20148,803,225'Tunneling field effect transistor having a lightly doped buried layer'20148,796,081'Semiconductor structure and method for forming the same'20148,785,938'Method for forming polycrystalline film, polycrystalline film and thin film transistor fabricated from the polycrystalline film'20148,786,017'Strained Ge-on-insulator structure and method for forming the same'20148,772,873'Ge-on-insulator structure and method for forming the same'20148,728,905'Stress-generating shallow trench isolation structure having dual composition'20148,704,306'Strained Ge-on-insulator structure and method for forming the same'20148,653,504'Complementary tunneling field effect transistor and method for forming the same'20148,653,574'Flash memory and method for fabricating the same'20148,642,414'MOS transistor structure with in-situ doped source and drain and method for forming the same'20148,592,864'Semiconductor device and method for forming the same'20138,588,176'System and method for performing handover in WiMAX mobile communication system'20138,587,029'Semiconductor structure and method for forming the same'20138,546,857'Semiconductor structure and method for forming the same'20138,492,846'Stress-generating shallow trench isolation structure having dual composition'20138,476,139'High performance MOSFET'20138,455,858'Semiconductor structure for reducing band-to-band tunneling (BTBT) leakage'20138,440,550'Method for forming strained layer with high Ge content on substrate and semiconductor structure'20138,299,540'High performance MOSFET'20128,227,316'Method for manufacturing double gate finFET with asymmetric halo'20128,149,933'Method and apparatus for subchannel assignment for suppressing interantenna interference in OFDMA system'20127,883,976'Structure and method for manufacturing device with planar halo profile'20117,829,939'MOSFET including epitaxial halo region'20107,750,658'Integrated circuit and testing circuit therein for testing and failure analysis'20107,704,844'High performance MOSFET'20107,678,638'Metal gated ultra short MOSFET devices'20107,494,861'Method for metal gated ultra short MOSFET devices'20097,476,579'Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film'20097,348,629'Metal gated ultra short MOSFET devices'20087,326,997'Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film'20087,183,613'Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2018Patents assigned to IBM (16)· patent assignee history
2007–2015Based in Beacon, NY, US· patent location history
2010–2013Based in Fishkill, NY, US· patent location history
2012–2015Patents assigned to WANG JING (28)· patent assignee history
2012–2019Based in Beijing, CN· patent location history
2013–2019Patents assigned to UNIV TSINGHUA (29)· patent assignee history
2013–2015Patents assigned to XU JUN (18)· patent assignee history
2013–2014Patents assigned to GUO LEI (12)· patent assignee history
2015–2020Based in San Jose, CA, US· patent location history
2021Based in Mountain View, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNIV TSINGHUA | 29 | 2013–2019 |
| WANG JINGself | 28 | 2012–2015 |
| XU JUN | 18 | 2013–2015 |
| IBM | 16 | 2007–2018 |
| GUO LEI | 12 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beijing, CN | 31 | 2012–2019 |
| San Jose, California, US | 10 | 2015–2020 |
| Beacon, New York, US | 9 | 2007–2015 |
| Fishkill, New York, US | 6 | 2010–2013 |
| Mountain View, California, US | 1 | 2021 |