Inventor

Darrell D. Boggs

Inventor

Aloha, OR, US

Overview

1995–2020

Patent span

Physics

Primary field (CPC G)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing100%

PatentTitleYear

10,642,744Memory type which is cacheable yet inaccessible by speculative instructions2020 9,891,972'Lazy runahead operation for a microprocessor'2018 9,875,105Checkpointed buffer for re-entry from runahead2018 9,823,931'Queued instruction re-dispatch after runahead'2017 9,740,553'Managing potentially invalid results during runahead'2017 9,632,976'Lazy runahead operation for a microprocessor'2017 9,563,432'Dynamic configuration of processing pipeline based on determined type of fetched instruction'2017 8,850,165'Method and apparatus for assigning thread priority in a processor or the like'2014 7,987,346'Method and apparatus for assigning thread priority in a processor or the like'2011 7,877,583'Method and apparatus for assigning thread priority in a processor or the like'2011 7,849,465'Programmable event driven yield mechanism which may activate service threads'2010 7,454,600'Method and apparatus for assigning thread priority in a processor or the like'2008 7,366,879'Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses'2008 7,353,370'Method and apparatus for processing an event occurrence within a multithreaded processor'2008 7,219,349'Multi-threading techniques for a processor utilizing a replay queue'2007 7,216,220'Microprocessor with customer code store'2007 7,200,737'Processor with a replay system that includes a replay queue for improved throughput'2007 7,181,598'Prediction of load-store dependencies in a processing agent'2007 7,089,409'Interface to a memory system for a processor having a replay system'2006 7,051,329'Method and apparatus for managing resources in a multithreaded processor'2006 7,039,794'Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor'2006 7,010,669'Determining whether thread fetch operation will be blocked due to processing of another thread'2006 6,981,129'Breaking replay dependency loops in a processor using a rescheduled replay queue'2005 6,889,319'Method and apparatus for entering and exiting multiple threads within a multithreaded processor'2005 6,877,086'Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter'2005 6,799,268'Branch ordering buffer'2004 6,779,103'Control word register renaming'2004 6,735,688'Processor having replay architecture with fast and slow replay paths'2004 6,665,792'Interface to a memory system for a processor having a replay system'2003 6,651,158'Determination of approaching instruction starvation of threads based on a plurality of conditions'2003 6,633,970'Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer'2003 6,591,344'Method and system for an INUSE field resource management scheme'2003 6,496,925'Method and apparatus for processing an event occurrence within a multithreaded processor'2002 6,467,027'Method and system for an INUSE field resource management scheme'2002 6,457,119'Processor instruction pipeline with error detection scheme'2002 6,385,715'Multi-threading for a processor utilizing a replay queue'2002 6,163,838'Computer processor with a replay system'2000 6,094,717'Computer processor with a replay system having a plurality of checkers'2000 6,041,403'Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction'2000 6,026,477'Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool'2000 5,974,523'Mechanism for efficiently overlapping multiple operand types in a microprocessor'1999 5,913,050'Method and apparatus for providing address-size backward compatibility in a processor using segmented memory'1999 5,740,393'Instruction pointer limits in processor that performs speculative out-of-order instruction execution'1998 5,687,338'Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor'1997 5,625,788'Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto'1997 5,581,717'Decoding circuit and method providing immediate data for a micro-operation issued from a decoder'1996 5,566,298'Method for state recovery during assist and restart in a decoder having an alias mechanism'1996 5,559,974'Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation'1996 5,537,560'Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor'1996 5,463,745'Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2014Patents assigned to INTEL CORP (42)· patent assignee history

1995–2018Based in Aloha, OR, US· patent location history

2014Patents assigned to ALLEN JAMES D (1)· patent assignee history

2014Patents assigned to BOGGS DARRELL D (1)· patent assignee history

2017–2020Patents assigned to NVIDIA CORP (7)· patent assignee history

2018Patents assigned to BOGGS DARRELL (1)· patent assignee history

2020Based in Hillsboro, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	42	1995–2014
NVIDIA CORP	7	2017–2020
ALLEN JAMES D	1	2014
BOGGS DARRELLself	1	2018
BOGGS DARRELL Dself	1	2014

Locations

Location	Patents	Span
Aloha, OR, US	49	1995–2018
Hillsboro, OR, US	1	2020