Inventor
Evgeni Gousev
Inventor
Saratoga, CA, US
Overview
Patents· 86 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices13%
G06FElectric digital data processing9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G02BOptical elements, systems or apparatus8%
G06KGraphical data reading7%
G06VImage or video recognition or understanding7%
H04NPictorial communication, e.g. television6%
B81BMicrostructural devices or systems, e.g. micromechanical devices4%
Y10TTechnical subjects covered by former us classification4%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems4%
PatentTitleYear
11,068,712Low-power iris scan initialization202110,984,235Low power data generation for iris-related detection and authentication202110,728,450Event based computer vision computation202010,667,706System and method for obtaining blood pressure measurement202010,667,705System and method for obtaining blood pressure measurement202010,614,332Light source modulation for iris size adjustment202010,534,074Hybrid scanning lidar systems202010,515,284Single-processor computer vision hardware control and application execution201910,478,858Piezoelectric ultrasonic transducer and process201910,408,926Implementation of the focal plane 2D APD array for hyperion lidar system201910,157,305Cover-glass optical isolation for optical touch and fingerprint sensing201810,115,671Incorporation of passives and fine pitch through via for package on package201810,116,868Display-integrated user-classification, security and fingerprint system201810,061,020Light detection and ranging (LIDAR) system with dual beam steering20189,986,211Low-power always-on face detection, tracking, recognition and/or analysis using events-based vision sensor20189,977,977Apparatus and method for low-power object-detection in images using computer vision feature computation hardware20189,923,004'Hardware acceleration of computer vision feature detection'20189,921,688'Large area interactive display screen'20189,870,506'Low-power always-on face detection, tracking, recognition and/or analysis using events-based vision sensor'20189,838,635Feature computation in a sensor element array20179,817,534'Illumination device with metalized light-turning features'20179,762,834'Configurable hardware for computing computer vision features'20179,582,725'Apparatus and method for low-power object-detection in images using image integration hardware'20179,582,117'Pressure, rotation and stylus functionality for interactive display screens'20179,554,100'Low-power always-on face detection, tracking, recognition and/or analysis using events-based vision sensor'20179,471,840'Apparatus and method for low-power object-detection in images using hardware scanning window'20169,454,265'Integration of a light collection light-guide with a field sequential color display'20169,325,420'Electro-optical transceiver device to enable chip-to-chip interconnection'20169,298,284'System and method for optically-based active stylus input recognition'20169,263,370'Semiconductor device with via bar'20169,182,851'Illumination device with metalized light-turning features'20158,970,516'Integrated passives and power amplifier'20158,922,974'MEMS varactors'20148,904,867'Display-integrated optical accelerometer'20148,866,757'Coated light-turning feature with auxiliary structure'20148,810,528'Illumination device with metalized light-turning features'20148,536,059'Equipment and methods for etching of MEMS'20138,492,874'High density metal-insulator-metal trench capacitor'20138,410,690'Display device with desiccant'20138,363,380'MEMS varactors'20138,323,516'Etching processes used in MEMS production'20128,222,066'Eliminate release etch attack by interface modification in sacrificial layers'20128,218,228'Two-terminal variable capacitance MEMS device'20128,193,051'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20128,164,815'MEMS cavity-coating layers and methods'20128,153,514'Method of forming metal/high-κ gate stacks with high mobility'20128,077,379'Interferometric optical display system with broadband characteristics'20117,978,395'Capacitive MEMS device with programmable offset voltage control'20117,928,514'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20117,887,711'Method for etching chemically inert metal oxides'20117,858,500'Low threshold voltage semiconductor device with dual threshold voltage control means'20107,785,999'Formation of fully silicided metal gate using dual self-aligned silicide process'20107,745,278'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics'20107,737,050'Method of fabricating a nitrided silicon oxide gate dielectric layer'20107,738,158'Electromechanical device treatment with water vapor'20107,733,552'MEMS cavity-coating layers and methods'20107,729,036'Capacitive MEMS device with programmable offset voltage control'20107,688,494'Electrode and interconnect materials for MEMS devices'20107,655,994'Low threshold voltage semiconductor device with dual threshold voltage control means'20107,643,203'Interferometric optical display system with broadband characteristics'20107,566,664'Selective etching of MEMS using gaseous halides and reactive co-etchants'20097,560,361'Method of forming gate stack for semiconductor electronic device'20097,479,683'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20097,452,767'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics'20087,369,292'Electrode and interconnect materials for MEMS devices'20087,326,610'Process options of forming silicided metal gates for advanced CMOS devices'20087,271,455'Formation of fully silicided metal gate using dual self-aligned silicide process'20077,242,055'Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide'20077,235,440'Formation of ultra-thin oxide layers by self-limiting interfacial oxidation'20077,202,186'Method of forming uniform ultra-thin oxynitride layers'20077,169,674'Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier'20077,105,889'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics'20067,078,300'Thin germanium oxynitride gate dielectric for germanium-based devices'20067,029,966'Process options of forming silicided metal gates for advanced CMOS devices'20066,958,506'High-dielectric constant insulators for feol capacitors'20056,891,231'Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier'20056,887,797'Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer'20056,667,207'High-dielectric constant insulators for FEOL capacitors'20036,642,156'Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics'20036,573,197'Thermally stable poly-Si/high dielectric constant material interfaces'20036,511,873'High-dielectric constant insulators for FEOL capacitors'20036,444,592'Interfacial oxidation process for high-k gate dielectric process integration'20026,436,196'Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer'20026,395,650'Methods for forming metal oxide layers with enhanced purity'20026,346,487'Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer'20026,287,897'Gate dielectric with self forming diffusion barrier'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2012Patents assigned to IBM (33)· patent assignee history
2001–2012Based in Mahopac, NY, US· patent location history
2006Based in Mohopac, NY, US· patent location history
2008–2018Patents assigned to QUALCOMM MEMS TECHNOLOGIES INC (22)· patent assignee history
2008–2021Based in Saratoga, CA, US· patent location history
2011–2013Patents assigned to GOUSEV EVGENI (8)· patent assignee history
2012–2014Patents assigned to GOUSEV EVGENI P (6)· patent assignee history
2013–2021Patents assigned to QUALCOMM INC (31)· patent assignee history
2013Based in San Jose, CA, US· patent location history
2019Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 33 | 2001–2012 |
| QUALCOMM INC | 31 | 2013–2021 |
| QUALCOMM MEMS TECHNOLOGIES INC | 22 | 2008–2018 |
| GOUSEV EVGENIself | 8 | 2011–2013 |
| GOUSEV EVGENI Pself | 6 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 54 | 2008–2021 |
| Mahopac, New York, US | 27 | 2001–2012 |
| San Diego, California, US | 1 | 2019 |
| San Jose, California, US | 1 | 2013 |
| Mohopac, New York, US | 1 | 2006 |