Inventor
Goh Matsuura
Inventor
Hartsdale, NY, US
Overview
Patents· 3 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices20%
PatentTitleYear
9,711,365'Etch rate enhancement for a silicon etch process through etch chamber pretreatment'20178,928,124'High aspect ratio and reduced undercut trench etch process for a semiconductor substrate'20158,652,969'High aspect ratio and reduced undercut trench etch process for a semiconductor substrate'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2017Patents assigned to IBM (3)· patent assignee history
2014–2017Patents assigned to ZEON CORP (3)· patent assignee history
2014Patents assigned to FULLER NICHOLAS C M (1)· patent assignee history
2014Patents assigned to JOSEPH ERIC A (1)· patent assignee history
2014Patents assigned to MATSUURA GOH (1)· patent assignee history
2014–2017Based in Hartsdale, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 3 | 2014–2017 |
| ZEON CORP | 3 | 2014–2017 |
| FULLER NICHOLAS C M | 1 | 2014 |
| JOSEPH ERIC A | 1 | 2014 |
| MATSUURA GOHself | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hartsdale, New York, US | 3 | 2014–2017 |