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Inventor

Maurice B. Steinman

Inventor
Marlborough, MA, US

Overview

49→
Patents
1991–2020
Patent span
Physics
Primary field (CPC G)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing58%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use26%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
H04LTransmission of digital information, e.g. telegraphic communication4%
G06TImage data processing or generation, in general1%
G11CStatic stores1%
H04JMultiplex communication1%
PatentTitleYear
10,671,722Mechanism for throttling untrusted interconnect agents202010,635,588Distributed coherence directory subsystem with exclusive data regions202010,223,162Mechanism for resource utilization metering in a computer system20199,423,847'Method and apparatus for transitioning a system to an active disconnect state'20169,417,679'Adaptive connected standby for a computing device'20169,360,906'Power management for multiple compute units'20169,261,949'Method for adaptive performance optimization of the soc'20169,043,625'Processor bridge power management'20159,021,209'Cache flush based on idle prediction and probe activity level'20158,966,305'Managing processor-state transitions'20158,959,372'Dynamic performance control of processing nodes'20158,924,758'Method for SOC performance and power optimization'20148,862,920'Power state management of an input/output servicing component of a processor system'20148,832,485'Method and apparatus for cache control'20148,656,198'Method and apparatus for memory power management'20148,645,639'Hierarchical memory arbitration technique for disparate sources'20148,566,628'North-bridge to south-bridge protocol for placing processor in low power state'20138,484,498'Method and apparatus for demand-based control of processing node performance'20138,412,971'Method and apparatus for cache control'20138,291,249'Method and apparatus for transitioning devices between power states based on activity request frequency'20128,266,389'Hierarchical memory arbitration technique for disparate sources'20128,176,352'Clock domain data transfer device and methods thereof'20128,156,362'Hardware monitoring and decision making for transitioning in and out of low-power state'20128,135,935'ECC implementation in non-ECC components'20128,112,648'Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state'20128,112,647'Protocol for power state determination and demotion'20127,957,428'Methods and apparatuses to effect a variable-width link'20117,941,683'Data processing device with low-power cache access mode'20117,870,407'Dynamic processor power management device and method thereof'20117,856,562'Selective deactivation of processor cores in multiple processor core systems'20107,844,767'Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link'20107,750,912'Integrating display controller into low power processor'20107,568,118'Deterministic operation of an input/output interface'20097,362,739'Methods and apparatuses for detecting clock failure and establishing an alternate clock lane'20087,200,770'Restoring access to a failed data storage device in a redundant memory system'20077,024,533'Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature'20066,920,512'Computer architecture and system for efficient management of bi-directional bus'20056,754,739'Computer resource management and allocation system'20046,704,817'Computer architecture and system for efficient management of bi-directional bus'20046,662,265'Mechanism to track all open pages in a DRAM memory system'20036,636,955'Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature'20036,622,225'System for minimizing memory bank conflicts in a computer system'20036,591,349'Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth'20036,546,453'Proprammable DRAM address mapping mechanism'20036,353,877'Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write'20026,128,711'Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes'20005,638,538'Turbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system bus'19975,559,987'Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system'19964,995,041'Write back buffer with error correcting capabilities'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2019Based in Marlborough, MA, US· patent location history
2000–2002Based in Marlboro, MA, US· patent location history
2003–2007Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (9)· patent assignee history
2010–2020Patents assigned to ADVANCED MICRO DEVICES INC (26)· patent assignee history
2012–2016Patents assigned to STEINMAN MAURICE B (15)· patent assignee history
2012–2015Patents assigned to BRANOVER ALEXANDER (11)· patent assignee history
2012–2014Based in Malborough, MA, US· patent location history
2012Based in Mailborough, MA, US· patent location history
2014–2016Patents assigned to BRANOVER ALEXANDER J (4)· patent assignee history
2020Based in Boxborough, MA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC262010–2020
STEINMAN MAURICE Bself152012–2016
BRANOVER ALEXANDER112012–2015
HEWLETT PACKARD DEVELOPMENT CO92003–2007
BRANOVER ALEXANDER J42014–2016
Locations
LocationPatentsSpan
Marlborough, Massachusetts, US391997–2019
Malborough, Massachusetts, US32012–2014
Boxborough, Massachusetts, US22020
Marlboro, Massachusetts, US22000–2002
Mailborough, Massachusetts, US12012