Inventor
ERIC CHIH-FANG LIU
Inventor
US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices38%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1036%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H10DInorganic electric semiconductor devices4%
H01JElectric discharge tubes or discharge lamps2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
12,588,262Sacrificial gate capping layer for gate protection during source/drain contact opening202612,568,677Method of self-aligned dielectric wall formation for forksheet application202612,564,027Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals202612,506,005—202512,482,702Wet etch process and methods to form air gaps between metal interconnects202512,451,354Double patterning method of patterning a substrate202512,451,353Double hardmasks for self-aligned multi-patterning processes202512,341,009Variable hardness amorphous carbon mask202512,265,326Method for reducing lithography defects and pattern transfer202512,237,216Method for filling recessed features in semiconductor devices with a low-resistivity metal202512,148,624Wet etch process and method to control fin height and channel area in a fin field effect transistor (FinFET)202412,100,598Methods for planarizing a substrate using a combined wet etch and chemical mechanical polishing (CMP) process202412,009,211Method for highly anisotropic etching of titanium oxide spacer using selective top-deposition202411,756,790Method for patterning a dielectric layer202311,651,965Method and system for capping of cores for self-aligned multiple patterning202311,557,479Methods for EUV inverse patterning in processing of microelectronic workpieces202311,424,123Forming a semiconductor feature using atomic layer etch202211,417,526Multiple patterning processes202211,333,968Method for reducing lithography defects and pattern transfer2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TOKYO ELECTRON LTD (19)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOKYO ELECTRON LTD | 19 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 19 | 2022–2026 |