Inventor
Shigeki Wada
Inventor
Tokyo, JP
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices17%
H04BTransmission13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
G03DApparatus for processing exposed photographic materials4%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner4%
H03FAmplifiers4%
H03HImpedance networks, e.g. resonant circuits4%
H03JTuning resonant circuits4%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
PatentTitleYear
8,571,095'Equalization filter and distortion compensating method'20138,170,093'Equalizing filter circuit'20127,983,370'Clock and data recovery circuit'20117,696,838'Equalizing filter circuit'20107,652,544'Voltage controlled oscillator and frequency control method of the voltage controlled oscillator'20107,529,595'Method of controlling substrate processing apparatus and substrate processing apparatus'20097,449,349'Processing schedule creating method, coating and developing apparatus, pattern forming apparatus and processing system'20087,183,853'Feedback amplifier having amplified signal path and feedback signal path separated'20077,167,769'Inline connection setting method and device and substrate processing devices and substrate processing system'20076,981,808'Substrate processing apparatus and substrate transferring method'20066,214,744'Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal'20016,087,256'Method for manufacturing modified T-shaped gate electrode'20006,008,136'Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2013Patents assigned to NEC CORP (8)· patent assignee history
1999–2013Based in Tokyo, JP· patent location history
2006–2009Patents assigned to TOKYO ELECTRON LTD (4)· patent assignee history
2006–2008Based in Kumamoto, JP· patent location history
2007Patents assigned to NEC ELECTRONICS CORP (1)· patent assignee history
2007Based in Minato-ku, JP· patent location history
2009Based in Koshi, JP· patent location history
2012–2013Patents assigned to WADA SHIGEKI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 8 | 1999–2013 |
| TOKYO ELECTRON LTD | 4 | 2006–2009 |
| WADA SHIGEKIself | 2 | 2012–2013 |
| NEC ELECTRONICS CORP | 1 | 2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 8 | 1999–2013 |
| Kumamoto, JP | 3 | 2006–2008 |
| Koshi, JP | 1 | 2009 |
| Minato-ku, JP | 1 | 2007 |