Inventor
Amitabh Jain
Inventor
Allen, TX, US
Overview
Patents· 68 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1035%
H01LSemiconductor devices9%
G06FElectric digital data processing2%
G06NComputing arrangements based on specific computational models2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H01JElectric discharge tubes or discharge lamps1%
B23KSoldering or unsoldering1%
C10MLubricating compositions1%
C10NIndexing scheme associated with subclass c10m relating to lubricating compositions1%
PatentTitleYear
11,038,827Message encoding and transmission across multiple platforms202110,726,374Risk prediction based on automated analysis of documents202010,696,919Lubricant dispersed with carbon nanotubes202010,483,261Integrated circuit having chemically modified spacer surface201910,409,805Clause discovery for validation of documents201910,162,850Clause discovery for validation of documents201810,068,802Threshold mismatch and IDDQ reduction using split carbon co-implantation20189,960,086Methods, apparatus and system for self-aligned retrograde well doping for finFET devices20189,620,423'Integrated circuit having chemically modified spacer surface'20179,496,359'Integrated circuit having chemically modified spacer surface'20169,245,975'Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length'20169,024,384'Indium, carbon and halogen doping for PMOS transistors'20158,987,748'Drain induced barrier lowering with anti-punch-through implant'20158,927,385'ZTCR poly resistor in replacement gate flow'20158,877,581'Strain-engineered MOSFETs having rimmed source-drain recesses'20148,865,549'Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length'20148,853,042'Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit'20148,772,118'Offset screen for shallow source/drain extension implants, and processes and integrated circuits'20148,691,644'Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor'20148,659,112'Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit'20148,580,663'Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams'20138,558,310'Indium, carbon and halogen doping for PMOS transistors'20138,372,750'Method and system for improved nickel silicide'20138,253,205'Method for forming strained channel PMOS devices and integrated circuits therefrom'20128,252,609'Curvature reduction for semiconductor wafers'20128,216,945'Wafer planarity control between pattern levels'20128,124,511'Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder'20128,125,035'CMOS fabrication process'20128,026,135'Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams'20117,932,139'Methodology of improving the manufacturability of laser anneal'20117,902,032'Method for forming strained channel PMOS devices and integrated circuits therefrom'20117,883,573'Method for preparing a source material for ion implantation'20117,825,025'Method and system for improved nickel silicide'20107,795,122'Antimony ion implantation for semiconductor components'20107,691,714'Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor'20107,678,637'CMOS fabrication process'20107,670,917'Semiconductor device made by using a laser anneal to incorporate stress into a channel region'20107,666,748'Method of forming amorphous source/drain extensions'20107,615,458'Activation of CMOS source/drain extensions by ultra-high temperature anneals'20097,557,022'Implantation of carbon and/or fluorine in NMOS fabrication'20097,557,021'Highly doped gate electrode made by rapidly melting and resolidifying the gate electrode'20097,511,350'Nickel alloy silicide including indium and a method of manufacture therefor'20097,494,905'Method for preparing a source material including forming a paste for ion implantation'20097,479,668'Source/drain extension implant process for use with short time anneals'20097,371,648'Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same'20087,355,255'Nickel silicide including indium and a method of manufacture therefor'20087,344,929'Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity'20087,345,355'Complementary junction-narrowing implants for ultra-shallow junctions'20087,344,985'Nickel alloy silicide including indium and a method of manufacture therefor'20087,306,995'Reduced hydrogen sidewall spacer oxide'20077,297,605'Source/drain extension implant process for use with short time anneals'20077,247,535'Source/drain extensions having highly activated and extremely abrupt junctions'20077,211,516'Nickel silicide including indium and a method of manufacture therefor'20077,173,296'Reduced hydrogen sidewall spacer oxide'20077,163,878'Ultra-shallow arsenic junction formation in silicon germanium'20077,118,980'Solid phase epitaxy recrystallization by laser annealing'20067,026,218'Use of indium to define work function of p-type doped polysilicon'20066,847,089'Gate edge diode leakage reduction'20056,812,073'Source drain and extension dopant concentration'20046,808,997'Complementary junction-narrowing implants for ultra-shallow junctions'20046,803,611'Use of indium to define work function of p-type doped polysilicon'20046,797,593'Methods and apparatus for improved mosfet drain extension activation'20046,743,705'Transistor with improved source/drain extension dopant concentration'20046,737,354'Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates'20046,713,360'System for reducing segregation and diffusion of halo implants into highly doped regions'20046,709,938'Source/drain extension fabrication process with direct implantation'20046,677,201'Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors'20046,482,688'Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2019Patents assigned to TEXAS INSTRUMENTS INC (62)· patent assignee history
2002–2004Based in Richardson, TX, US· patent location history
2004–2019Based in Allen, TX, US· patent location history
2012–2016Patents assigned to JAIN AMITABH (13)· patent assignee history
2012–2016Patents assigned to KIRKPATRICK BRIAN K (3)· patent assignee history
2012–2014Patents assigned to NANDAKUMAR MAHALINGAM (3)· patent assignee history
2018–2020Patents assigned to ICERTIS INC (3)· patent assignee history
2018–2020Based in Pune, IN· patent location history
2020Based in Navi Mumbai, IN· patent location history
2021Based in Aurora, IL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 62 | 2002–2019 |
| JAIN AMITABHself | 13 | 2012–2016 |
| ICERTIS INC | 3 | 2018–2020 |
| KIRKPATRICK BRIAN K | 3 | 2012–2016 |
| NANDAKUMAR MAHALINGAM | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Allen, Texas, US | 56 | 2004–2019 |
| Richardson, Texas, US | 6 | 2002–2004 |
| Pune, IN | 3 | 2018–2020 |
| Aurora, Illinois, US | 1 | 2021 |
| Navi Mumbai, IN | 1 | 2020 |