Inventor
Subarnarekha Sinha
Inventor
Menlo Park, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
Y02PClimate change mitigation technologies in the production or processing of goods19%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices17%
G05BControl or regulating systems in general3%
G06TImage data processing or generation, in general3%
G06VImage or video recognition or understanding3%
H01HElectric switches3%
H10DInorganic electric semiconductor devices3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
PatentTitleYear
9,098,649'Distance metric for accurate lithographic hotspot classification using radial and angular functions'20158,601,419'Accurate process hotspot detection using critical design rule extraction'20138,578,313'Pattern-clip-based hotspot database system for layout verification'20138,566,754'Dual-purpose perturbation engine for automatically processing pattern-clip-based manufacturing hotspots'20138,490,030'Distance metric for accurate lithographic hotspot classification using radial and angular functions'20138,452,075'Range pattern matching for hotspots containing vias and incompletely specified range patterns'20138,219,941'Range pattern definition of susceptibility of layout regions to fabrication issues'20128,209,639'Identifying layout regions susceptible to fabrication issues by using range patterns'20128,205,179'Fast evaluation of average critical area for IC layouts'20128,205,185'Fast evaluation of average critical area for IC layouts'20128,141,007'Method and apparatus for identifying and correcting phase conflicts'20128,006,212'Method and system for facilitating floorplanning for 3D IC'20118,000,826'Predicting IC manufacturing yield by considering both systematic and random intra-die process variations'20117,962,882'Fast evaluation of average critical area for IC layouts'20117,962,873'Fast evaluation of average critical area for ic layouts'20117,703,067'Range pattern definition of susceptibility of layout regions to fabrication issues'20107,679,872'Electrostatic-discharge protection using a micro-electromechanical-system switch'20107,543,255'Method and apparatus to reduce random yield loss'20097,509,622'Dummy filling technique for improved planarization of chip surface topography'20097,503,029'Identifying layout regions susceptible to fabrication issues by using range patterns'20097,496,883'Method and apparatus for identifying and correcting phase conflicts'20097,346,865'Fast evaluation of average critical area for IC layouts'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2015Patents assigned to SYNOPSYS INC (22)· patent assignee history
2008–2012Based in Foster City, CA, US· patent location history
2009–2013Based in Menlo Park, CA, US· patent location history
2012–2013Patents assigned to SINHA SUBARNAREKHA (9)· patent assignee history
2012–2013Patents assigned to CHIANG CHARLES C (7)· patent assignee history
2012Patents assigned to SU QING (2)· patent assignee history
2013Patents assigned to KWANG KENT Y (2)· patent assignee history
2013–2015Based in Palo Alto, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNOPSYS INC | 22 | 2008–2015 |
| SINHA SUBARNAREKHAself | 9 | 2012–2013 |
| CHIANG CHARLES C | 7 | 2012–2013 |
| KWANG KENT Y | 2 | 2013 |
| SU QING | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Menlo Park, California, US | 11 | 2009–2013 |
| Foster City, California, US | 8 | 2008–2012 |
| Palo Alto, California, US | 3 | 2013–2015 |