Inventor

Niteen A. Patkar

Inventor

Sunnyvale, CA, US

Overview

21→

Patents

1997–2007

Patent span

Physics

Primary field (CPC G)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing95%

G01RMeasuring electric variables5%

PatentTitleYear

7,263,642'Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system'2007 7,013,456'Profiling execution of computer programs'2006 6,941,545'Profiling of computer programs executing in virtual memory systems'2005 6,826,748'Profiling program execution into registers of a computer'2004 6,775,756'Method and apparatus for out of order memory processing within an in order processor'2004 6,745,318'Method and apparatus of configurable processing'2004 6,701,426'Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets'2004 6,643,726'Method of manufacture and apparatus of an integrated computing system'2003 6,578,134'Multi-branch resolution'2003 6,449,671'Method and apparatus for busing data elements'2002 6,430,646'Method and apparatus for interfacing a processor with a bus'2002 6,389,519'Method and apparatus for providing probe based bus locking and address locking'2002 5,966,530'Structure and method for instruction boundary machine state restoration'1999 5,751,985'Processor structure and method for tracking instruction status to maintain precise state'1998 5,708,788'Method for adjusting fetch program counter in response to the number of instructions fetched and issued'1998 5,675,759'Method and apparatus for register management using issue sequence prior physical register and register association validity information'1997 5,659,721'Processor structure and method for checkpointing instructions to maintain precise state'1997 5,651,124'Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state'1997 5,649,136'Processor structure and method for maintaining and restoring precise state at any instruction boundary'1997 5,644,742'Processor structure and method for a time-out checkpoint'1997 5,632,028'Hardware support for fast software emulation of unimplemented instructions'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–1998Patents assigned to HAL COMPUTER SYSTEMS INC (6)· patent assignee history

1997–2006Based in Sunnyvale, CA, US· patent location history

1998–1999Patents assigned to FUJITSU LTD (2)· patent assignee history

2002–2006Patents assigned to ATI INT SRL (10)· patent assignee history

2007Patents assigned to AZUL SYSTEMS INC (1)· patent assignee history

2007Based in Burlingame, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ATI INT SRL	10	2002–2006
HAL COMPUTER SYSTEMS INC	6	1997–1998
FUJITSU LTD	2	1998–1999
AZUL SYSTEMS INC	1	2007

Locations

Location	Patents	Span
Sunnyvale, California, US	20	1997–2006
Burlingame, California, US	1	2007