Inventor
Sang-Beom Kang
Inventor
Hwaseong-si, KR
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores72%
G06FElectric digital data processing8%
H10BElectronic memory devices5%
H10DInorganic electric semiconductor devices2%
H10NElectric solid-state devices not otherwise provided for2%
A41BShirts1%
A47GHousehold or table equipment1%
A47LDomestic washing or cleaning1%
B31DMaking articles of paper, cardboard or material worked in a manner analogous to paper, not provided for in subclasses b31b or b31c1%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
PatentTitleYear
10,446,207Spin transfer torque magnetic random access memory for supporting operational modes with mode register201910,204,670Spin transfer torque magnetic random access memory for supporting operational modes with mode register20199,183,910'Semiconductor memory devices for alternately selecting bit lines'20159,147,500'Semiconductor memory device having resistive memory cells and method of testing the same'20159,042,152'Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device'20158,780,617'Semiconductor memory device and method of performing burn-in test on the same'20148,780,656'Stacked memory device and method of repairing same'20148,711,649'Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same'20148,677,216'Stacked semiconductor memory device and related error-correction method'20148,654,595'Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters'20148,611,121'Stacked memory devices'20138,589,767'Systems, devices and methods using redundant error correction code bit storage'20138,422,328'Semiconductor device, semiconductor system including the same, and voltage supply method of semiconductor device'20138,406,029'Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices'20138,374,052'Information storage devices using magnetic domain wall movement and methods of operating the same'20138,369,173'Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same'20138,355,291'Resistive memory device and method of controlling refresh operation of resistive memory device'20138,345,464'Resistive memory devices having a stacked structure and methods of operation thereof'20138,279,667'Integrated circuit memory systems and program methods thereof including a magnetic track memory array using magnetic domain wall movement'20128,271,856'Resistive memory devices and methods of controlling operations of the same'20128,248,842'Memory cell array biasing method and a semiconductor memory device'20128,238,148'Semiconductor device having architecture for reducing area and semiconductor system including the same'20128,228,711'Bi-directional resistive memory devices and related memory systems and methods of writing data'20128,223,529'Resistive memory devices, memory systems and methods of controlling input and output operations of the same'20128,144,535'Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same'20128,136,017'Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method'20128,111,563'Multi-level nonvolatile memory device with fast execution of program speed and programming method of the same'20128,054,665'Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers'20118,050,079'Nonvolatile memory device using variable resistive element'20118,050,074'Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices'20118,031,517'Memory device, memory system having the same, and programming method of a memory cell'20117,994,493'Phase change memory devices employing cell diodes and methods of fabricating the same'20117,993,961'Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines'20117,924,639'Nonvolatile memory device using resistance material'20117,920,405'Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices'20117,907,467'Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof'20117,903,448'Resistance random access memory having common source line'20117,894,236'Nonvolatile memory devices that utilize read/write merge circuits'20117,869,256'Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto'20117,859,882'Resistive memory device and method of writing data'20107,843,716'Nonvolatile memory device having memory and reference cells'20107,843,715'Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods'20107,808,811'Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof'20107,751,234'Phase change memory device and program method thereof'20107,724,560'Nonvolatile memory device having twin memory cells'20107,710,767'Memory cell array biasing method and a semiconductor memory device'20107,701,747'Non-volatile memory including sub cell array and method of writing data thereto'20107,589,367'Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines'20097,586,775'Nonvolatile memory device and related method of operation'20097,586,776'Nonvolatile memory devices having multi-filament variable resistivity memory cells therein'20097,570,511'Semiconductor memory device having a three-dimensional cell array structure'20097,542,356'Semiconductor memory device and method for reducing cell activation during write operations'20097,522,449'Phase change memory device and related programming method'20097,515,459'Method of programming a memory cell array using successive pulses of increased duration'20097,499,306'Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range'20097,471,553'Phase change memory device and program method thereof'20087,457,151'Phase change random access memory (PRAM) device having variable drive voltages'20087,436,693'Phase-change semiconductor memory device and method of programming the same'20087,436,711'Semiconductor memory device'20087,427,531'Phase change memory devices employing cell diodes and methods of fabricating the same'20087,391,669'Semiconductor memory device and core layout thereof'20087,352,616'Phase change random access memory, boosting charge pump and method of generating write driving voltage'20087,349,245'Non-volatile phase-change memory device and associated program-suspend-read operation'20087,317,655'Memory cell array biasing method and a semiconductor memory device'20087,280,391'Phase change memory device for use in a burst read operation and a data reading method thereof'20077,262,990'Semiconductor memory device'20077,190,607'Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (66)· patent assignee history
2007–2019Based in Hwaseong-si, KR· patent location history
2007–2012Based in Gyeonggi-do, KR· patent location history
2007Based in Seoul, KR· patent location history
2010–2014Based in Yongin-si, KR· patent location history
2012–2015Patents assigned to KANG SANG-BEOM (14)· patent assignee history
2012–2015Patents assigned to PARK CHUL-WOO (10)· patent assignee history
2012–2013Patents assigned to KANG SANG BEOM (9)· patent assignee history
2012–2013Patents assigned to KIM HO JUNG (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 66 | 2007–2019 |
| KANG SANG-BEOMself | 14 | 2012–2015 |
| PARK CHUL-WOO | 10 | 2012–2015 |
| KANG SANG BEOMself | 9 | 2012–2013 |
| KIM HO JUNG | 9 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hwaseong-si, KR | 53 | 2007–2019 |
| Yongin-si, KR | 7 | 2010–2014 |
| Gyeonggi-do, KR | 6 | 2007–2012 |
| Seoul, KR | 1 | 2007 |