Inventor
John Banning
Inventor
Sunnyvale, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
8,924,648'Method and system for caching attribute data for matching attributes with physical addresses'20148,566,564'Method and system for caching attribute data for matching attributes with physical addresses'20138,549,266'System and method of instruction modification'20138,473,727'History based pipelined branch prediction'20138,438,548'Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version'20138,370,604'Method and system for caching attribute data for matching attributes with physical addresses'20137,984,277'System and method of instruction modification'20117,979,669'Method and system for caching attribute data for matching attributes with physical addresses'20117,904,891'Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur'20117,779,241'History based pipelined branch prediction'20107,725,656'Braided set associative caching techniques'20107,698,539'System and method of instruction modification'20107,644,210'Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system'20107,617,088'Interpage prologue to protect virtual address mappings'20097,404,181'Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold'20087,380,098'Method and system for caching attribute data for matching attributes with physical addresses'20087,249,246'Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions'20077,111,096'Fast look-up of indirect branch destination in a dynamic translation system'20067,096,460'Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation'20067,089,397'Method and system for caching attribute data for matching attributes with physical addresses'20066,845,353'Interpage prologue to protect virtual address mappings'20056,640,297'Link pipe system for storage and retrieval of sequences of branch addresses'20036,615,300'Fast look-up of indirect branch destination in a dynamic translation system'20036,594,821'Translation consistency checking for modified target instructions by comparing to original copy'20036,363,336'Fine grain translation discrimination'20024,794,524'Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2014Based in Sunnyvale, CA, US· patent location history
2002–2008Patents assigned to TRANSMETA CORP (11)· patent assignee history
2009–2013Patents assigned to BANNING JOHN (6)· patent assignee history
2010–2013Patents assigned to BANNING JOHN P (6)· patent assignee history
2010–2013Patents assigned to COON BRETT (4)· patent assignee history
2011–2013Patents assigned to ANVIN H PETER (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TRANSMETA CORP | 11 | 2002–2008 |
| BANNING JOHNself | 6 | 2009–2013 |
| BANNING JOHN Pself | 6 | 2010–2013 |
| ANVIN H PETER | 4 | 2011–2013 |
| COON BRETT | 4 | 2010–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 26 | 1988–2014 |